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To: Tony Viola who wrote (15837)10/26/1998 10:14:00 PM
From: patrick tang  Respond to of 25814
 
Reminds of 'upstairs-downstairs' - the 'haves' vs the 'have-nots' - IP that is. To do SOC is not easy. LSI is at the front of the game.

Now if it can just turn that into earnings .....

patrick



To: Tony Viola who wrote (15837)10/26/1998 10:16:00 PM
From: patrick tang  Read Replies (1) | Respond to of 25814
 
Read in San Jose Mercury talking about wide-spread cable modem deployment in South Bay and 2COM cable modems at Fry's this X'mas - well, all that new 0.25um stuff's coming, 0.35um need not apply.

patrick



To: Tony Viola who wrote (15837)10/27/1998 10:00:00 AM
From: Moonray  Respond to of 25814
 
LSI Logic Completes USB CoreWare(R) Family With New Host and Hub Cores
PRNewswire - 09:15 a.m. Oct 27, 1998 Eastern

MILPITAS, Calif., Oct. 27 /PRNewswire/ -- Two
highly-configurable cores that enable designers to create
system-level ASICs with the industry-standard universal system
bus (USB) interface were introduced today by LSI Logic (NYSE:
LSI) as part of the company's CoreWare(R) library. A new Host
Core allows the connection of USB-enabled peripherals to
embedded system platforms, and a new Hub Core provides the
ability to expand the number of USB connections in host-attached
peripherals.

The two new cores complement a previously introduced USB
CoreWare component, a Function Core that provides the USB
interface for peripheral devices such as printers and scanners.
The now complete USB core family will enable designers to
develop system-level ASICs with USB peripheral connectivity
for embedded systems addressing consumer applications such as
telephony, digital cameras, as well as handheld computers.

First developed for use with personal computers, USB is an
emerging industry-standard bus architecture that supports 'hot
swapping', the ability to add or delete a peripheral without
shutting down and restarting a system. With hot swapping, the
host system automatically detects the peripheral and configures
the necessary software. The USB architecture will ultimately
replace the multiple incompatible low-bandwidth serial and
parallel I/O ports with a single type of connection.

"USB's consumer friendly plug-and-play interface enables the
development of exciting new products that will accelerate the
convergence of the PC and consumer markets," said Scott
Hudson, senior analyst at Cahners In-Stat Group. "Users will be
able to easily connect next-generation, Internet-capable set-top
boxes, video games, digital cameras, and video conferencing
systems to PC's and widely-available, inexpensive PC
peripherals, such as printers, joysticks, keyboards. By using LSI
Logic's new cores and CoreWare methodology, developers can
easily add USB interfaces to new consumer products and PC
peripherals."

Steve Whalley, USB Implementers Forum chairman said, "LSI
Logic's expertise in high integration ASIC cores and digital audio
and video will contribute to the rapid adoption of USB by further
reducing the time-to-market and increasing the performance of
future USB product offerings."

Core Family Speeds USB ASIC Time to Market

The Host, Hub and Function cores are fully USB compliant.
Provided in a highly configurable architectures, the cores can be
modified to meet specific customer requirements. Each core is
offered in a "firm" implementation as a fixed netlist with layout
and timing guidelines. This approach provides ample flexibility,
allowing the physical design layout to be easily modified while
maintaining USB functionality and timing closure.

LSI Logic also offers USB transceivers in the I/O libraries. Fully
compliant to the USB specification, the transceivers operate in
both full- and low-speed modes, enabling fully- integrated
single-chip systems.

To simplify design integration, the cores are provided in both
encrypted RTL and unencrypted SCAN-inserted netlist forms.
RTL speeds the development of the system ASIC architecture at
the behavior simulation level, while the netlist accelerates the
structural implementation. With an optimized, proven, fixed
netlist in LSI Logic's ASIC technology, designers can
concentrate on other value-added aspects of the system ASIC. By
using these RTL and netlist formats, the development and
prototyping of a large system-on-a-chip design incorporating
USB, MIPs, PCI, and Ethernet cores was completed in less than
a year from design conception.

Host Core Adds USB Connectivity to a Wide Range
of Systems

The OHCI- and USB -compliant Host Core connects
USB-enabled peripherals to a host system. It generates and
manages the Universal Serial Bus host interface and establishes
communications between the host system and USB peripherals
and is configurable to support from 1 to 15 root hub ports. The
Host Core can be integrated into core logic for workstations and
PCs and a wide variety of embedded systems such as set-top
boxes and Windows CE-based palm-size and handheld personal
computers.

Designers configure the core by answering a series of questions
presented in a configuration utility, which generates synthesizable
RTL based from the designer input. The Host Core's default
configuration provides two Root Hub ports; however, it can be
configured to support up 15 root hub ports.

Hub Core Adds USB Flexibility

The Hub Core provides the critical ability to add peripherals to
USB-enabled systems and detect connections and removals. It
can be configured to support from 1 to 15 downstream ports for
use with both low- and full-speed peripheral devices. The Hub
Core typically will be used with high-end printers, multifunction
peripherals, CRT monitors and flat-panel displays.

The default design supports four ports, however, it can be
configured to support from 1-15 ports. Designers configure the
Hub Core through a configuration utility, which generates
synthesizable RTL from a worksheet completed by the designer.

"The USB cores blend the best attributes of soft and hard
macrocell core implementations resulting in a very flexible
CoreWare solution," said Larry Przywara, product marketing
manager at LSI Logic. "In addition to being easy to implement,
the LSI Logic USB CoreWare family has been exhaustively
verified, comes with complete documentation and is proven in
LSI Logic's ASIC technologies. This allows designers to
concentrate on value-added engineering without being concerned
with USB compatibility or timing issues, accelerating the
development of their differentiated USB system ASICs."

Price and Availability

The USB cores are available today in the CoreWare library. They
are priced only in the context of a complete CoreWare
system-on-a-chip design, not as an individual core or component.

About LSI Logic

LSI Logic Corporation, the System on a Chip Company(R), is a
leading supplier of custom high-performance semiconductors,
with operations worldwide. The company enables customers to
build complete systems on a single chip with its CoreWare(R)
design program, thereby increasing performance, lowering
system costs and accelerating time to market. LSI Logic develops
application-optimized products in partnership with trendsetting
customers, and operates leading-edge, high-volume
manufacturing facilities to produce submicron chips. LSI Logic is
headquartered at 1551 McCarthy Boulevard, Milpitas, California
95035, 408-433-8000, www.lsilogic.com.

Reader inquiries should be directed to 800-574-4286 within the
US and Canada, or 32-11-300351 within Europe, or
408-433-7700 for all other countries. Ask for Dept. CPNR14

NOTE: The LSI Logic logo design, CoreWare and The System
on a Chip Company are registered trademarks of LSI Logic
Corporation. All other brand or product names may be
trademarks or registered trademarks of their respective companies
SOURCE LSI Logic Corporation

Copyright 1998, PR Newswire

o~~~ O