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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Joey Smith who wrote (40210)	10/27/1998 2:54:00 PM
From: Maxwell	Respond to of 1573215

Die Size, 0.25um, and 0.18um Processes: Company....Technology...........SRAM Cell Size ------------------------------------------- Intel......P856.5 (0.25um)...........9.3um^2 Intel......P858 (0.18um)............~6.0um^2 IBM........CMOS-7S (0.22um)..........6.8um^2 IBM........CMOS-8S (0.18um)..........4.2um^2 MOT........HIP 5 (0.22um)............7.6um^2 MOT........HIP 6 (0.18um)............4.5um^2 AMD........CS44E (0.25um)...........~7.0um^2 AMD........CS50 (0.18um)............~4.2um^2 IBM, MOT, and AMD are all using the same process from IBM with local interconnect (LI). LI helps in reducing the SRAM cell size tremendously. Intel P856.5 process is currently Intel most advanced 0.25um process which is used for the PII-450 and CeleronA. Had LI is used then the SRAM cell size can be shrunk another 25%. This is where AMD will have an advantage over Intel when it comes to integrating L2 cache on chip. Furthermore as the technology is scaled down the process which gets the LI gets the advantage. Maxwell