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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (40515)	10/31/1998 3:27:00 PM
From: Scumbria	Respond to of 1573713

Tench, If the problem is memory latency, wouldn't the multi-cycle L1 latency of the K7 be a step backwards? The multi-cycle latency is due to the fact that the CPU is becoming faster than the cache. Multi-cycle latencies are inevitable as we approach 1 GHz. It is a very serious problem for all CPU architectures, but particularly bad for x86 because operands are kept in memory (rather than the register file.) Pipelining to the L1 mitigates the additional latency, but once again is aggravated by the complexity of x86. Scumbria