SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Scumbria who wrote (40518)10/31/1998 6:47:00 PM
From: RDM  Respond to of 1573737
 
I thank you for your clarification of the response cycle of the L2 cache. My description was clearly too simplistic and aroused quite a
response on this thread because many people are studying the details of the cache architecture quite carefully.

However, the major point that I was trying to express was that the
K6-3 is the only K6 for the future higher clocked applications because the K6-2 is beginning to suffer greatly in throughput at
clock frequency above 400 Mhz from cache "issues". The K6-2 will be
relegant to "Celeron competition" or other cost sensitive roles or discontinued as the clock rates go to 600 Mhz and above.