SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Tenchusatsu who wrote (40593)11/1/1998 9:10:00 PM
From: Ali Chen  Read Replies (2) | Respond to of 1573696
 
Ten, <many engineers would disagree with your statement that the multiprocessor bus is old-fashioned compared to multiple P2P connections.> Should you say "many engineers at Intel would
disagree" I would agree. Otherwise, who people should
trust more - Intel's guys who have no experience in
scalable multiprocessing whatsoever, or former Digital
engineers who have built lots of highest-performing
systems? Should I mention 4X-Xeon again, or ..?

<but once again, cache coherency is going to require additional latency cycles.> It looks like Intel is above all
those cache coherency problems, does not it? As
usual, above all:)

<By the way, Intel decided that Merced should go onto an SMP bus. According to you, they must be out of their minds to put new IA-64 technology on an "old-fashioned" bus.>
Why not? Whose minds you are talking about?
When Intel was cut off from the high-scalable Digital
party due to indecent behavior (as you know, they
had a look at Alpha design but decided not to
pay for the ideas), they have nothing to do
but invent their own "bus". So much for Intel's
"creativity", and smells like new iAPX-432...



To: Tenchusatsu who wrote (40593)11/1/1998 9:28:00 PM
From: kash johal  Read Replies (2) | Respond to of 1573696
 
Tench,

>Re: Perhaps you can tell us how server OEM's are going to create >4-way K7 chipsets without adding a crossbar, thus adding additional l>atency. Do you think that one north bridge chip will support four >P2P connections? Perhaps you can have two north bridges each >supporting two P2P connections, but once again, cache coherency >is going to require additional latency cycles. Or maybe the 4-way K7 >will go for a non-uniform memory architecture.

Those are excellent questions.

I guess a guide might be how Alpha does 2-way,4-way, 8-way etc systems as the K7 follows that architecture and likely will follow the ALpha philosophy.

Perhaps you could enlighten us on how Alpha's do it.

Regards,

Kash