An interesting article - Why CMP is becoming essential
semibiznews.com
Semiconductor Business News, © 1998, CMP Media Inc.
November 1, 1998
Once considered a black art, planarization is needed for shrinking device geometries and the move to copper
By J. Robert Lineback
It has taken a long time for some U.S. chip makers to make the switch to CMP, or chemical mechanical polishing. But now, they need major improvements in the process to turn out new generations of chips.
Asian DRAM makers managed to "design out" CMP for their current generation of chips, but they won't be able to avoid it much longer. For some emerging chip technologies, CMP absolutely will be required, according to process developers.
Wafer fab managers understandably were nervous about using CMP in the beginning. It took plenty of nerve to place partly processed wafers face down in a solution of silica or alumina and then grind them flat for the next process step. But it worked, and more and more fabs are using CMP now as device geometries shrink below a quarter micron and layers of interconnect grow.
"If you had shown a fab manager [CMP] 10 years ago, he'd have thought you were crazy," said Gino Addiego, vice president and general manager of the CMP division at Applied Materials Inc. in Santa Clara, Calif. "It's a process that people initially believe won't work," he said. "But sure enough, it does planarize the surface and the device yields are great."
"For years, CMP was more or less considered a 'black art,'" noted Robert N. Castellano, president of The Information Network in New Tripoli, Pa. "But now there is less concern about damaging or losing wafers."
"Today," the analyst said, "a lot more is understood about the dozen or so parameters involved in planarizing wafers [with CMP tools]. These include the movement of wafers, the speed of platens, the pH of solutions, additives, and the type of pads used inside the tools," he said. "But people are still on the learning curve," he pointed out.
Planarization is becoming a critical factor in the photolithography steps for making transistors in the front-end-of-the-line (FOEL) processes. With device feature sizes dropping to 0.18 micron and below, the depth of field in lithography also shrinks. This makes the ultra-smooth surfaces that CMP can turn out a crucial requirement in the fabrication of shallow-trench isolation structures and polygates.
CMP also is rapidly becoming a mainstay in the production of microprocessors and complex ASICs. More U.S. chip makers are turning to it to ease the task of stacking metal interconnect layers on top of one another. Just ahead, fab experts predicted, CMP technology and integrated wafer cleaning systems will be absolutely required in dual-damascene processing of next-generation copper and low-k dielectric interconnect structures.
As the industry gains confidence and learns more about CMP, tool suppliers are attempting to improve and tweak the technology by changing the way that these tools work. Lam Research Corp. and Silicon Valley startup Aplex Inc., for example, are each promoting new CMP tool architectures that polish layers away with fast-moving belts, like a sander.
Other CMP suppliers are working on improving conventional rotary polishers that turn wafers on spinning platens. Integrated Process Equipment Corp. (IPEC) in Phoenix, which took an early lead this decade in "round-and-round" CMP polishers, has introduced an orbital polishing technique that it claimed will reduce the equipment footprint, cut the use of slurry solutions, and produces greater uniformity across the planarized wafer surface.
Next-door rival SpeedFam Corp. in Chandler, Ariz., upped the ante in the mid-1990s by launching a multi-head polisher that speeded throughput by planarizing five wafers in parallel. Now a new concept called fixed-abrasive polishing is emerging as chip manufacturers look for ways to improve polishing precision yet reduce the cost of expensive consumables such as slurry solutions.
Pioneering this approach is startup Obsidian Inc. in Fremont, Calif., which turned out to be one of the hottest chip industry startups this year. It attracted $16.3 million in second-round venture capital in the second quarter this year for pursuing this technology (SBN, Sept. 1, p. 12). Obsidian's system would do away with the need for slurries. But the startup will not likely be alone in offering such a fixed-abrasive system because nearly all major CMP suppliers said that they were working on similar concepts.
"You can't afford not to be looking into fixed abrasives," said Kazi Heinik, director of marketing for IPEC Planar in Phoenix.
There is a major hurdle remaining, however. The slurryless, fixed-abrasive CMP system's polishing pads have a relatively short lifetime, according to some tool managers. They can cost more than several thousands of dollars each. "Right now, [pad lifetime] can be as little as 300 wafers," estimated Steve McGrady, director of international marketing and business development at SpeedFam, which is trying to develop this type of system.
The use of such advanced wafer planarization technologies is now being pushed hard by early adopters such as IBM, Intel, and Motorola, but Asian memory makers and foundries are still wrestling with the task of putting CMP to work in volume production.
Part of their problem is that CMP isn't cheap. In fact, it is considered to be one of the most expensive new chip processes of the '90s. Integrated CMP polishers and cleaners can cost up to $2.5 million a pop. In a high-volume wafer fab, as many as 20 systems can reside in a CMP bay. CMP slurry costs per tool run up to $200,000 a year. By the time everything is added up -- capital equipment, slurry solutions, DI water, and polishing pads -- the cost for CMP technology averages between $15 to $30 per wafer, according to industry estimates.
It now costs about $12 to send a single wafer pass through a CMP tool for planarization, according to a recent study by O'Mara & Associates in Palo Alto, Calif. That cost is expected to decline gradually to about $10 a wafer by 2003, the study predicted.
Chip makers also are struggling to cut the growing costs of consumables. O'Mara & Associates estimated that DI water consumption in CMP ranges from 10 to 20 gallons per wafer. The industry target calls for that to be cut by two-thirds over the next few years.
Companies also want to cut the consumption of slurry. "You are seeing big pressures on the tool makers to get the use of slurry down to 100 milliliters where it used to be fine to use a liter," said Willy Krusell, vice president of the CMP Division at Lam in Fremont, Calif.
The potentially higher cost of consumables played a major role in Lam's decision to use standard polishing pads and slurries in its Linear Planarization Technology. The company claims that this system achieves unequal radial velocities with a belt platen module that's capable of linear speeds of 400-to-600 feet per minute. "We don't have to play games to get good results," said Krusell, referring to the linear belt approach to polishing wafers.
But other CMP suppliers strongly disagreed, saying they also can achieve the same results and speeds using rotary polisher architectures. Applied, for example, has developed a new head concept that increases the platen speeds to 150-to-200 revolutions per minute vs. the 30 rpms that other systems run. "This duplicates the velocities claimed by Aplex and Lam," maintained Applied's Addiego. "We don't think a different kind of architecture really buys you anything."
Lam and Aplex disagree, of course. Lam's Krusell maintained that results from the linear belt approach are easier to predict. "All of the vectors are going in one direction," he said. Lam claims that belt tools inherently offer greater pattern insensitivity (three times better than rotary systems), higher removal rates at lower pressure, and greater overall stability.
Aplex, which is backed by investors from Asia and Japan, is planning to introduce its AVera CMP polisher at Semicon Japan in December. Production units should become available by the end of 1999. The system is being targeted aggressively at next-generation processes, shallow-trench isolation applications, and the huge new CMP market opportunity in Asia. "Introducing the system in Japan is a strategically important to us," noted Rick LaFrance, vice president of sales and customer service at the two-year-old Sunnyvale, Calif., firm.
Until now, struggling DRAM makers and cost-conscious foundries in Asia have managed to work around the problems needing higher degrees of planarization in processes. But many experts believe that time is running out on them and CMP technology is due to take off in the Far East.
"Asian DRAM manufacturers have been able to 'design out' CMP through the 256-megabit generation, but it eventually will be required," stated SpeedFam's McGrady. "The Far East has been taken out [of the growth cycle] in recent years, but it will be the next big opportunity for CMP. You will probably see something on the order of 60% growth in the Far East [for CMP] during the next two or three years," he predicted.
Shipments of CMP polishing gear will dip about 3% worldwide to $350 million in 1998 from $360 million in 1997, according to market forecasts made by The Information Network. This slight dip in revenues follows two big years of CMP growth -- 40% last year and 56% in 1996, according to the market researcher.
Shipments of post-CMP cleaning tools also are expected to slip in 1998 to $95 million, down from $110 million in 1997. But chemical mechanical polishing segment overall is expected to take off again next year, according to analyst Castellano.
The next round of growth in CMP investments will be due to several factors, but led by the growing number of wafers being processed in deep submicron technologies. But more process steps are beginning to require planar surfaces, and wafers must often make multiple passes through CMP tools to get the desired results. One of the biggest potential boosts for CMP use is expected to come from dual-damascene processing copper and low-k dielectric interconnect structures.
"With the advent of dual-damascene processing, CMP becomes an absolute necessity, no longer just an option for yield enhancement," declared Paul Winebarger, director of the interconnect program at Sematech in Austin, Tex.
But dual-damascene processing of copper interconnects is one of the biggest challenges for CMP tools and their associated cleaning systems. To begin with, CMP gear must be able to precisely remove metal instead of the interconnect insulators that is the case in today's interlevel dielectric level (IDL) oxide polishing applications.
"This is analogous to IDL tungsten polishing, but you are taking away the overfill of copper from the trenches and via holes," Winebarger said. "You must selectively take away the copper, but stop when you hit the dielectric and not dish or thin out any of the trenches. You also don't want to thin out the dielectric layer, either," he added.
Another concern is the clean up after the copper is removed from the wafer. Post-CMP cleaning systems will have to get all of the corrosive metal from the wafers before they move on to other processing tools. Otherwise, major portions of fabs could become contaminated by unwanted copper particles.
The need for greater precision in tools is causing CMP suppliers to expand their options for end-point detection systems, real-time control, and in situ metrology. "Integrating metrology tools in situ makes the systems more robust," said Applied Materials' Addiego.
The hope here is to be able to not only measure wafers as they complete CMP polishing but also feed back the results to control systems which would help to adjust the tool setting for the next batch of wafers. Applied recently added a second in situ metrology option to its Mirra CMP systems that measure layer thickness while the wafers are still wet and inside the tool. They use an embedded system from Israel's Nova Measuring Instruments Ltd. A dry measurement system from Nanometrics Inc. in Sunnyvale, Calif., also is available to compare pre- and post-polishing thickness.
Other vendors are using a variety of end-point detection techniques to determine precisely when polished layers are flat enough for Post-CMP cleaning and the next process steps. IPEC, for example, is offering both the Nova metrology system and an in situ end-point detection system from Luxtron Corp of Santa Clara, Calif., that measures the motor current in CMP tools to determine when a particular layer of metal or oxide is removed.
One expectation with the new fixed abrasive technologies is that system performance will become more predictable because the impact of consumable variations will be reduced. "One of the biggest issues today in CMP is understanding the stability of consumables -- both the slurries and polishing pads," said Sematech's Winebarger. "The hope is that fixed abrasives might help in that area."
If they do, the soaring costs of CMP tools can be held down by reducing the need for sophisticated detectors, metrology systems, and control systems. Improving the predictable performance of tools also will help.
The integration of polishers with dedicated post-CMP cleaning systems also has helped to improve results by eliminating the chance that wet slurry solutions will dry on the surface of wafers. Improving CMP tool speeds did that. "Older systems did not have the throughput speeds to justify a dedicated cleaning system," said Applied's Addiego. Today, however, most CMP tools run at about 60 wafers an hour, making it feasible to attach a cleaning system to the equipment for "dry in/dry out" solutions.
Cleaning tools also are playing a role in reducing defects (tiny polishing scratches) from the wafers. "One goal we have is to push the responsibility of defect removal back onto the scrubbers [inside cleaners]," said John de Larios, vice president of cleaning technology at On-Trak Systems, a San Jose-based subsidiary of Lam. "Many customers today do a buff [a step inside the polisher], but the long-term strategy is to develop new cleaning technologies and processes that reduce the burden on the polisher," he said. |
