SANTA CLARA, Calif.--(BUSINESS WIRE)--Nov. 16, 1998--Clear Logic
today announced a new Laser-Processed Logic Device (LPLD(TM))
technology that will allow it to provide pin-compatible replacements
of Altera(R)'s (NASDAQ:ALTR) MAX(R) 7000 CPLDs for as little as half
the price Altera charges.
Clear Logic's LPLD technology can cut over 1 million transistors
from its largest (512 macrocell) MAX 7512A replacement, reducing die
size by as much as 60%.
Clear Logic expects to introduce its first LPLD product families,
the CL7000, CL7000E, and CL7000S, in the first quarter of 1999, to
replace Altera MAX 7000, MAX 7000E, and MAX 7000S devices.
According to Don Knowlton, Clear Logic's vice president of
marketing, "Our development of the CL7000 architecture confirms that
our technology can be applied to create low cost replacements for any
Altera architecture.
"With our first product family, the CL8000, introduced early this
year, we achieved an enormous die size reduction by eliminating the
transistors in the SRAM-based configuration elements used for routing
Altera FLEX 8000 devices. Since CPLDs don't have the same
configuration elements, our design team had to come up with a new
approach. They have achieved outstanding results."
Dr. Joseph Chiang, Clear Logic's vice president of design and the
leader of the LPLD design team said, "Basically, we evaluated every
aspect of the Altera MAX 7000 architecture to locate and eliminate
transistors that are not necessary when our laser fuse technology is
used for configuration. First, we eliminated every transistor in the
interconnect array, but we felt we needed to go further to achieve the
smallest possible die size and fastest possible speeds.
"Next, we discovered that if we also architected the product term
AND array in a new way, we could eliminate 80% of the AND array
transistors required in Altera MAX 7000 devices. This was a big
breakthrough for us. Overall, we have cut the total number of
transistors by more than a million in the highest density 512
macrocell devices when compared to Altera's programmable
implementation.
"A big benefit of this approach is that it also cut the bit-line
capacitance by 40%. The CL7000 LPLD devices will have lower power
consumption, shorter delays, and better noise immunity, as well as a
smaller die," Chiang concluded.
Knowlton explained, "Getting an LPLD from Clear Logic will be
exactly like getting a pre-programmed PLD from your distributor --
only the Clear Logic parts will cost less, consume less power, and be
faster. The customer provides Clear Logic with a MAX 7000 bitstream
file or a programmed part.
"Within two weeks, Clear Logic delivers first articles for
customer-verification. Within four weeks, we deliver production
volumes of the laser-configured CL7000 device. That's comparable to
the lead-times for pre-programmed PLDs from distributors.
"With the advent of the new CL7000 architecture, Clear Logic has
demonstrated our commitment to fulfill our original promise to
introduce a broad array of convenient, lower-cost production
alternatives for Altera's popular products. And we're not done yet! In
the future, we are going to introduce laser-configured replacements
for other Altera architectures," Knowlton stated.
LPLD Technology Provides Full Altera MAX 7000 Compatibility With
40% - 60% Less Silicon
Clear Logic's LPLD technology employs the same types of logic
resources as do Altera MAX 7000 CPLDs (including product-term
macrocells and a central interconnect array) so the functionality and
pinout of Clear Logic devices and Altera MAX 7000 devices are
identical.
In fact, for any customer design, the Altera MAX 7000 bitstream
will be ported directly to the new Clear Logic alternative without any
modification, and the CL7000 product will function identically.
Clear Logic's laser-configured technology takes up much less
silicon than a programmable architecture, with the result that die
sizes of CL7000 LPLDs will be up to 60% smaller than those of
corresponding Altera MAX 7000 devices. Huge numbers of transistors
were eliminated in both the interconnect and product term AND arrays.
Laser-configured Interconnect Array
The LPLD architecture replaces Altera's Programmable Interconnect
Array (PIA) with a Laser-configured Interconnect Array (LIA). In each
place where Altera has a connection point in its PIA, Clear Logic's
LIA uses a single metal fuse that replaces the function of eleven
transistors used in the Altera architecture. Since the LIA has no
transistors, it requires 70% less silicon area than does Altera's
equivalent PIA, with attendant improvements in capacitance, speed, and
power.
Product Term AND Array
The LPLD architecture uses only a single transistor and three
metal fuses for each input term, while the Altera MAX 7000
architecture requires six transistors per input term. Thus, Clear
Logic can implement the product term AND array in 55% less silicon,
further reducing the bit-line capacitance and delays, and providing
substantial improvements in noise immunity.
Embedded Test Circuitry
The LPLD architecture is segmented into small blocks, called
TestCells(TM). Each TestCell contains scan registers that operate only
when activated by a test mode and can be scanned through the I/O pins.
During bitstream file extraction, Clear Logic's NoFault(TM) test
vector generation tool automatically generates test vectors that are
derived from the customer's bitstream, and provides 100% fault
coverage. Unlike CPLDs, CL7000 devices are fully tested at the Clear
Logic factory, in the customer's configuration, with 100% fault
coverage.
1,000,000 Fewer Transistors Than the Largest Altera MAX 7000
Overall, the Clear Logic architecture eliminates more than 1
million of the transistors required to achieve the same functionality
as the highest density Altera device, the MAX 7512A. All CL7000 family
members will offer very large reductions in transistor count. Among
other benefits, the much lower transistor count will enable the
company to charge radically lower prices for its parts, compared to
programmable logic devices.
All in all, Clear Logic will achieve numerous competitive
advantages from the new technology.
CMOS Process Provides Better Costs
Altera MAX 7000 CPLDs are fabricated using an EEPROM process
technology. This is a high cost process with many steps. Clear Logic's
CL7000 families of devices are fabricated using a standard CMOS
process which is cheaper, has fewer steps and provides excellent
yields, contributing to an already substantial cost advantage.
Laser Fuses Offer Better Scalability
As process technologies shrink, die size reductions are not
necessarily linear. Since the thin oxide transistors used in Altera
MAX 7000 CPLDs must be able to withstand high programming voltages,
their size cannot be reduced proportionately with the process.
The CL7000 laser-fuses are directly scalable so that shrinking
the process will result in a proportional die size reduction in CL7000
devices. This means that as process technologies continue to shrink,
Clear Logic will improve its cost advantage over Altera MAX 7000
devices.
40% Less Bit-Line Capacitance
The elimination of approximately 40% of the bit line transistors
in the product term AND array of the CL7000 architecture cuts bit-line
capacitance by 40%, providing designers with better performance and
power consumption margins, while improving noise immunity.
Better Performance
The speed path of a product term based PLD architecture is
determined by the amount of capacitance in the product term AND array
bit-lines, the delay of the interconnect array, and the sense
amplifier. By reducing both the bit-line capacitance and the
interconnect array delay, the Clear Logic architecture provides
shorter internal timing delays. Clear Logic management believes that
it may be able to offer the world's fastest product term-based logic
device at a future date.
Comparable to Ordering Pre-programmed Parts
CL7000 LPLD devices arrive from the Clear Logic factory fully
configured and 100% tested with the customer's design. Since there is
no programming step when using CL7000 LPLD devices, there are no bent
leads or other damage normally associated with pre-programmed CPLDs.
Unlike in-system programmable (ISP) devices, no expensive testers
are required and board assembly can be done automatically without
slowing down the line for the programming process. Programming
failures do not occur.
No Risk Option
Clear Logic distributors will accept orders for as few as one
tube or one tray of units. Thus, there is none of the inventory risk
that is associated with ASIC implementations. Design modifications are
accommodated by simply sending the revised bitstream file to Clear
Logic.
Clear Logic will hold blank CL7000 inventories that will be
available to be laser-configured with the correct customer pattern as
needed -- in much the same way that distributors hold inventories of
blank CPLDs that are to be pre-programmed when required.
Product Road Map
During 1999, Clear Logic intends to introduce several families of
LPLD devices that will support all Altera MAX 7000, MAX 7000S, MAX
7000E and MAX 7000A CPLD products with 96 or more macrocells. CL7000
LPLDs will be available in all the speed grades, supply voltages, and
production packages currently offered by Altera. The first CL7000
devices will be introduced during the first quarter of 1999.
Clear Logic, Inc. was founded in 1996 to offer a no-NRE, quick
turn-around cost reduction path for designs that have been implemented
using Altera programmable logic products. The company employs
proprietary software that converts the bitstream from an Altera design
to a laser-configured device. Clear Logic has no NRE charges or
minimum order sizes.
Called Laser-Processed Logic Devices or LPLDs, Clear Logic
devices are comparable to pre-programmed CPLDs, with comparable
delivery lead-times. They arrive at the customer's site fully
pre-configured and ready to plug in the socket. Clear Logic LPLD
devices are guaranteed to function identically to their programmable
counterparts.
CONTACT: Clear Logic
John Beekley, 408/988-5688
beekley@clear-logic.com
or
The William Baldwin Group
Nancy B. Green, 650/856-6192
nbg@william-baldwin.com |
