SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Elmer who wrote (41181)11/10/1998 3:03:00 PM
From: Ali Chen  Read Replies (2) | Respond to of 1571040
 
<Does this mean Sharpy will have a backside bus and L3 controller on board?>
This only means that the M. Kanellos is a stinking
pro-Intel moron in technical matters. And you and Pal are
blind followers..

Wasn't that you who tried to teach us here how to
count pins on processors?



To: Elmer who wrote (41181)11/10/1998 3:22:00 PM
From: Paul Engel  Read Replies (2) | Respond to of 1571040
 
Elmer - Re: " Does this mean Sharpy will have a backside bus and L3 controller on board????? Would the MB cache then be L4??"

My guess is that the L3 cache refers to an external cache and the L3 cache controller would somehow default to the Chip Set cache controller (L2 becomes L3) ?

Maybe that idea is delaying the Sharpy ???!!!

Paul