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To: John Rieman who wrote (37214)11/12/1998 12:01:00 AM
From: Maya  Read Replies (1) | Respond to of 50808
 
Electronica: Fujitsu demos MPEG-2 decoder
By Junko Yoshida
EE Times
(11/10/98, 4:14 p.m. EDT)

MUNICH, Germany — Fujitsu Mikroelektronik GmbH, showed off Fujitsu's first MPEG-2 Main Profile @ High Level decoder chip at Electronica this week. The device was developed in partnership with Heinrich-Hertz-Institute (HHI) of Berlin, which provided the algorithm for the chip.

The commercially available HiPEG MPEG-2 decoder, which was developed as an ASIC, started life “as a pure research project with HHI more than two-and-a-half years ago to demonstrate how our ASIC technology can handle such a complex algorithm on a single chip,” said Guenther Junge, ASIC marketing manager at Fujitsu Mikroelektronik (Dreieich-Buchschlag, Germany). In the course of the project, “we recognized that this can be a significant chip that Fujitsu can sell both in the U.S. and Japanese markets,” Junge said.

The HiPEG decoder is capable of decoding all 18 video formats specified by the U.S. Advanced Television Systems Committee (ATSC), and any video streams up to1,440 progressive and 1,920 interlaced technology. The device can handle picture frequencies of both 50 Hz (required for Europe) and 60 Hz (required for the United States). The HiPEG chip also provides a 3/2 pull-down feature, but as a pure decoder, and it does not come with a display processor.

“There is still a lot of room for our product to play,” Junge said, even as a number of U.S., European, Japanese and Korean companies have rushed to launch high-definition decoder chips. “Many companies have made a lot of announcements on their product plans, but the only commercial MPEG-2 MP@HL ICs out on the market today are those by LG Semicon, STMicroelectronics and Mitsubishi/Lucent,” he said. “To make an HD decoder with such complexities without bugs is not an easy task.”

Fujitsu's chip has already won a design-win in a U.S. professional video product, Junge said.

To bring the chip down to a consumer market, Fujitsu and HHI need to develop a more highly integrated chip that uses less memory and consumes less power. The HiPEG chip demonstrated Tuesday (Nov. 10) at Electronica was made in a 0.35-micron CMOS process and uses 128 Mbit of SDRAM. It operates on a 3.3-volt supply and dissipates 2.5 watts of power. The chip, shown on a demonstration board, was encased in a heat-sync package with a fan.

Fujitsu plans to introduce a newer version of HiPEG built in a 0.25-micron process and integrating a demux capability by April 1999.

Back in Japan, Fujitsu is separately preparing a dedicated audio DSP capable of handling 15 different audio decoding algorithms, Junge said. “Our plan is to integrate the audio DSP into HiPEG some time later next year.”

Fujitsu expects to use a 0.25-micron DRAM-logic process to integrate DRAM right into the HiPEG chip by mid 2000, according to Fujitsu's product road map.

HHI will need to develop a new algorithm for Fujitsu's future consumer-friendly HiPEG solution

eetimes.com



To: John Rieman who wrote (37214)11/12/1998 12:17:00 PM
From: view  Read Replies (1) | Respond to of 50808
 
John/David;

can you explain how ESST is able to attack several markets (VCD, DVD, SVCD, MODEM, PC Audio, SET-UPS) with 1/3 of Cube's R&D.



To: John Rieman who wrote (37214)11/12/1998 12:56:00 PM
From: DiViT  Respond to of 50808
 
Toshiba Processor May Be Brains Of PlayStation
Anthony Cataldo and David Lammers

11/12/98
CMP TechWeb
Copyright 1998 CMP Media Inc.


Sony Computer Entertainment and Toshiba will soon announce research on a jointly developed media processor that may provide the first glimpse at the embedded hardware for the next version of Sony's wildly successful PlayStation.

At the International Solid State Circuits Conference next February, the companies will together present two papers describing a multimedia processor. Although neither company would comment on how their development work will play out in the market, rumors have been swirling for some time that they have been cooperating on a next-generation game console. The ISSCC papers offer the first peek at jointly developed silicon that could be used for such a platform.

PlayStation is a coveted system win among IC makers, and Toshiba's coup reflects that company's growing prowess in the system-on-a-chip era. But the high-profile work apparently will not bump LSI Logic Inc. (LSI) out of its PlayStation sockets.

Elie Antoun, an LSI vice president in charge of consumer IC product development, said his understanding is Toshiba silicon will reside alongside ASICs from LSI Logic in the next go-round.

"I can't exactly comment, but the anecdotal evidence is Toshiba silicon may be in there, too," said Antoun, who until last summer, was president of LSI Logic's Japan subsidiary. "I am highly confident ASICs from LSI will be there. We are designing something quite significant that will go in that [next-generation] box, but who else is in the box I cannot say."

Although LSI Logic, in Milpitas, Calif., may continue to be a player, it appears the company may not dominate the next-generation PlayStation the way it did the first, introduced about five years ago. At that time, the gut-wrenching effects produced by the driving game Ridge Racer, combined with the silicon from LSI, took the game market by storm.

At the Interactive Digital Media Association convention in Orlando, Fla., last month, a Sony representative said the company is making an astounding 2 million PlayStations a month. Having dropped the hardware price to $129, Sony makes much of its overall profits by licensing and selling games to run on the CD-based system.

Performance Refresh In one ISSCC paper, Toshiba and Sony will describe a 17-by-14.1-millimeter device consisting of a 250-MHz MIPS CPU core with 128-bit multimedia extensions, 10 floating-point multiplier accumulators (MACs), four floating-point dividers, an MPEG-2 decoder, a 10-channel DMA controller, and other peripherals -- all linked together by 128-bit internal buses.

The 0.18-micron, 1.8-V device packs 10.5 million transistors and dissipates 15 watts.

The second paper describes in more detail the 10.9-by-6.3-mm CPU block that is the nucleus of the multimedia chip. This MIPS-compatible CPU is a two-way, superscalar architecture with 8 kilobytes of D-cache, 16 KB of I-cache, and 1-k-by-128 bits of scratch-pad RAM tightly coupled to the pipe and 128-bit internal data paths. The CPU is capable of executing more than 100 multimedia instructions.

"The embedded MPU processor was developed by Toshiba, and the interface technology was developed by Sony," said Yoichi Unno, general manager of Toshiba's microelectronics engineering laboratory. He said Toshiba and Sony have had a working relationship for the past three years.

Unno would not comment on whether the media processor was intended for Sony's next-generation game console, but he did say the two companies intend to make a public announcement in February regarding their partnership. A Toshiba spokesman said the announcement could come weeks before ISSCC or during the conference, which will be held in San Francisco Feb. 15 to 17, 1999.

Because ISSCC prohibits companies from fully disclosing papers before the their formal presentation, no further details about the chip's features were publicly available.

Even so, the basic description indicates an architecture that uses both hardwired, distributed processing and software-based processing. It makes wide use of hardwired blocks such as independent MACs and a separate MPEG-2 decoder connected by wide 128-bit internal buses, yet it also leverages the CPU to execute special multimedia instructions.

Such a heavy reliance on CPU power would be a departure from Sony's single-chip device, co-developed with LSI Logic. That part has been described by those involved as an exemplary case of a distributed-processing design.

Even though it uses a relatively slow 34-MHz CPU, the processor in the original PlayStation is able to eke out 220 MIPS by placing much of the burden on bus and memory-access channels to enable simultaneous operation among the various functional blocks. A separate graphics processing unit brings the total processing power to 500 MIPS.

However, in the four years since the last PlayStation hardware architecture came to light, advances in process technology and CPU speeds have made software-oriented computing more practical. The use of multimedia instructions, as described in the ISSCC summary, would indicate a greater reliance on CPU power.

Indeed, Toshiba engineers have said they are starting to put more weight on utilizing the power of faster on-chip CPU to carry much of the processing load rather than relying solely on dedicated functional blocks. Such a sentiment has been echoed by engineers at companies such as NEC.



In a recent interview, Toshiba engineers outlined a plan to couple hardwired intellectual-property blocks and embedded software designed to take advantage of fast embedded MPUs as the best recipe for system-on-a-chip design.

"We're going to provide hardware and software intellectual-property cores in parallel," said Atsushi Tanaka, a specialist with the intellectual-property planning section of Toshiba's IC Center, in Kawasaki, Japan, a division of the microelectronics group working with Sony. "The performance of the MPU is increasing rapidly, and every year, more and more tasks can be accomplished by software."

As for graphics, neither of the two ISSCC papers from Toshiba and Sony makes mention of 3-D processing functionality, which could indicate those tasks will fall to a separate processor. That would make sense, because any high-performance 3-D engine is probably still too transistor-laden to be absorbed into a general-purpose media processor, said Michito Kimura, an analyst with International Data Corp. (IDC), in Tokyo.

"I think the chip size would be too big," he said. "Maybe it will be possible by 2002 or 2003."

What is known about Sony's 3-D plans is the company will depart from polygon-based 3-D graphics now used in the PC world. Instead, it will develop a new generation of real-time image-rendering technologies that will encompass a new breed silicon, platform algorithms, and software titles.

There's also strong evidence that by including an MPEG-2 decoder engine on-chip, Sony may be aiming to incorporate video-processing, such as DVD , in its future platform. The company already uses optical-disk media for PlayStation, and some believe moving to DVD would be a natural next step.

"The new trend will be DVD versions of game consoles," said IDC's Kimura.

Kimura added Sony's group has been vocal about its desire to couple embedded DRAM with 3-D processing, another area where Toshiba has strength.

When it dropped out of the three-way DRAM venture co-sponsored by IBM and Siemens, Toshiba brought back a group of DRAM design engineers and put many of them to work on developing a "merged" DRAM-in-logic process. Toshiba has used that technology in its ASIC business. Also, the company has converted a DRAM fab at its complex in Oita, Japan, and upgraded it to 0.25-micron merged process capabilities.

LSI Logic, too, is working on embedded DRAM, in tandem with Micron Technology, in Boise, Idaho. With the development phase drawing to an end, LSI said it expects to have merged DRAM capabilities in its arsenal by mid-1999. But that may be too late for the chip set being developed for the next-generation PlayStation.

Sources said Toshiba initially got its foot in the door at Sony, the most sought-after electronics customer among Japan's IC companies, after it was chosen to design a gate array that now serves as glue logic in the current PlayStation.

Toshiba's apparent success in working with Sony for such a high-profile consumer product is a testament to how strong a contender Toshiba's system-on-a-chip business has become in recent years.

"Toshiba is and will be a major player and is a formidable force in system-on-a-chip," said Jan Goodsell, a Tokyo-based consultant who represents third-party intellectual-property suppliers. "They have huge resources and work well with a lot of third parties. They have the technical resources and a lot of intellectual property."

Nearly every IC vendor covets the Sony PlayStation business. When Brian Halla, CEO of National Semiconductor, took the stage at the Microprocessor Forum in San Jose, Calif., last month, he immediately asked Ken Kutaragi, in charge of chip development at Sony Computer Entertainment, to stand up and take a bow.