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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (41527)	11/16/1998 2:44:00 AM
From: Tenchusatsu	Respond to of 1574258

<This should have minimal performance impact for K7. Remember that K7 has a 128K L1 (4X the size of the current Xeon's and PII's.) A few clocks extra latency going off chip for L1 misses will not be devastating to performance. Obviously it would be better to have the L2 onboard, but the large L1 will nullify most of the impact.> Heh, I'm still trying to figure out how AMD can have an oversized L1 cache and still run their K7 CPU at high frequencies. Perhaps that large L1 cache has some longer latencies, and AMD figured that a smaller miss rate offsets the longer latency. If that's the case, and the miss rate is smaller, then the K7 isn't going to need that L2 cache as much as the Pentium II, like you said. Of course, the L2 cache is much more useful in multiprocessor configurations. <Bandwidth from the L2 is not very important for performance of single processor systems. Data is only moved one cache line at a time, never in large blocks which would make the bandwidth a significant factor.> Pipelining the transactions will effectively cause multiple cachelines to be moved at a time. And with all those deep buffers, theoretically the K7 will need to pipeline those cache reads like crazy. Realistically, well, we're talking about x86 code here. Tenchusatsu