SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Maxwell who wrote (41573)11/16/1998 6:17:00 PM
From: Scumbria  Read Replies (3) | Respond to of 1572507
 
Maxwell,

The current standard is 100MHz SDRAM. It is cheap and plenty.

The latency for an SDRAM page hit is 25ns, and about 100ns for a page miss. You can add as many execution units as you want, but it will not fix the fundamental problem of data starvation.

Having multiple execution units is like driving a Porsche during rush hour. You get home at about the same time you would in a VW bus, because the maximum speed is mostly irrelevant for normal usage.

Scumbria



To: Maxwell who wrote (41573)11/16/1998 7:18:00 PM
From: Tenchusatsu  Read Replies (1) | Respond to of 1572507
 
<G) L3 cache>

That's a new one. When did AMD ever announce an L3 cache for K7? I thought that AMD might just pull the L2 cache from off-chip to on-die sometime in the near future, but I really doubt that AMD would want to implement both an on-die L2 cache and an off-chip L3 cache.

Tenchusatsu


HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News