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To: Fred Fahmy who wrote (68639)11/16/1998 9:23:00 PM
From: MR. PANAMA (I am a PLAYER)  Read Replies (1) | Respond to of 186894
 
I wonder what the losses are on the short side here ...those who shorted after listening to all that DESTRUCTIVE and MONTHLY OPTION WEEK DRIBBLE....

This was a PERSECUTION of INTEL not just a downgrade along da way....



To: Fred Fahmy who wrote (68639)11/16/1998 9:27:00 PM
From: MR. PANAMA (I am a PLAYER)  Respond to of 186894
 
Item Ticker Company Name Month Shares Short Avg Daily Volume Ratio* Remark
1 INTC   Intel Corporation
10/98 17,675,820 17,435,422 1.01  
09/98 18,200,962 23,317,589 0.78  
08/98 20,867,333 17,406,006 1.20  
07/98 26,386,002 17,343,433 1.52  
06/98 33,892,855 16,337,257 2.07  
05/98 24,967,168 15,127,219 1.65  



To: Fred Fahmy who wrote (68639)11/17/1998 1:22:00 AM
From: Paul Engel  Read Replies (2) | Respond to of 186894
 
Fred - Re: " Scum's observation over the last 17 months. "

Scumbria has been WRONG as much as Kurlak !

Well, he (Scumbria) did get in to AMD at $15 2/3 but before that, I think he took a bath on the way down from $48 !

Paul



To: Fred Fahmy who wrote (68639)11/17/1998 2:21:00 AM
From: Paul Engel  Respond to of 186894
 
Fred & Intel Invetsors - Intel's Flash Memory Business Update

Here's a look into the status of Intel's Flash Memory Business.

Note the upcoming 0.18 micron process and 128 MegaBit, 2.7 volt StrataFlash product.

Paul

{========================}
edtn.com

Top Technology Story: EE Times

Intel flash move could put
wafer-level packages on the map

By Anthony Cataldo

TOKYO — In a move that could spur a migration toward
next-generation chip-scale packaging, Intel Corp. plans to
begin producing flash memory devices using wafer-level
packages by next year. The devices will be used for
applications that demand smaller size and weight, said
Hans Geyer vice president and general manager of Intel.

The company also plans to offer a range of new boot-block
and multilevel cell-flash devices in the coming year as it
tweaks its plan to convert to a 0.25-micron process in order
to save costs, and begins development of 0.18-micron
process technology.

Intel's endorsement of the wafer-level packaging should
boost the nascent technology. Intel is the leading
manufacturer of flash devices and was among the first to
embrace microBGA chip-scale packaging. The company
claims it is the largest supplier of flash microBGAs.

Wafer-level packaging, also known as wafer-scale, takes
chip-scale packaging a step further by doing away with the
plastic encasement and attaching the solder balls directly
onto the die.

"The attractiveness is that you can save several processing
steps and materials" to reduce package costs, Geyer said.
Intel can save between 10 and 20 cents in packaging costs
for each chip, which is a significant reduction, he said.

Intel is studying how to reduce the risk of the relatively rigid
wafer-level packages coming loose after they are soldered
onto a pc board. Intel will probably look to form a
partnership with a company that has packaging expertise.

"The complexity is in the soft elastomer between the die
and the solder balls," Geyer said. "The moment you bend it,
there is a lot of rigidity. It's not a trivial problem. We may
need to look at various kinds of underflow that acts as a
buffer between the die and solder ball."

Geyer does not expect wafer-level-packaged chips to be
used in applications across the board. They are most
suitable for consumer applications that place a premium on
size and weight, and that are redesigned often enough so
they are not affected by packaging configurations that
change with die sizes. Cellular phones, which make up the
largest portion of Intel's flash business, would be one such
application, he said.

Packaging has emerged as a central issue for flash
manufacturers, particularly in Japan. Many companies here
that have embraced chip-scale packaging are now taking
the concept to the extreme. Mitsubishi recently announced
a 59.5-mm2 molded chip-scale package for flash
memories and SRAMs that is less than half the size of a
48-lead TSOP-I. Hitachi Ltd. introduced a 0.75-ball-pitch
thin fine-pitch ball-grid array (TFBGA) package that takes
up half the area of a TSOP-II.

Japanese IC suppliers have been pushing for more
widespread use of multichip module packages that house
flash and SRAM. Sharp and Mitsubishi agreed to
cooperate on stacked-CSP; Fujitsu, NEC and Toshiba are
working together on an incompatible stacked-MCP. And
Hyundai and Samsung have weighed in with their own MCP
specification.

Geyer said Intel has recognized the trend toward multichip
packages combining SRAMs and flash memories, but the
company is still evaluating what approach it will take.
Because of the mechanical issues related to matching the
SRAMs and flash chips and the lack of a clear MCM
standard, it may not make sense to settle on one approach.

"There is no standard today," he said. "The other thing is
that when you want to combine two parts — one flash, one
SRAM — there are some mechanical constraints. The
SRAM has to have the size and bond-pad layout that is
comparable with flash, so the customer can only use so
many SRAMs. Yet customers want different flash vs. SRAM
sizes. How much do you limit that flexibility?"

As it weighs its packaging options, Intel has started
preliminary work on 0.18-micron flash technology. By year's
end, Geyer said, Intel should tape out its first test chip so it
can examine the memory array, logic structure and sense
amps.

Meanwhile, the company plans to add several products to
its flash lineup. Next year, it will introduce its first 3-V
StrataFlash memory device, which employs multilevel cell
technology to store two bits of data per flash cell, as well as
a 128-Mbit version of the device family. Geyer said Intel has
more than 100 design wins for its 32- and 64-Mbit devices,
spread among a wide number of embedded applications
such as set-top boxes, scanners, networking equipment
and office-automation equipment.

By the first half, Intel will introduce an 8-Mbit version of its
fast boot-block (F3) family to complement its current
16-Mbit device. Designed for direct execution of code, the
device can be configured to interface to any MCU without
the need for glue logic. Data is transferred in either
asynchronous page mode or synchronous burst mode at 54
MHz without wait states.

Intel is also selling samples of a new 0.25-micron, 2.7-V
32-Mbit advanced boot-block device (C3). Designed to
prevent code piracy in cellular phones, the device splits the
OTP register into two 64-bit sectors containing Intel factory
code and customer-specific code that can be scrambled
using software routines.

Despite a steadily growing demand for flash, Geyer said
prices have continued to decline and will probably not
recover until 2000. Since 1996, Intel's average selling
prices have fallen from more than $7 to a little more than $3
today.

"The overall flash market is ugly, and it's highly likely the
market will drop in revenue this year," he said. "Most
suppliers are spending less on capacity and R&D. I don't
expect ASPs to turn around until the second half of 1999 or
2000. I think we'll come out of this downturn slightly behind
DRAMs."

Even so, Intel said it was able to post higher revenue for the
first three quarters of the year and gain market share over
competitors, Geyer said. According to Dataquest Inc. (San
Jose, Calif.), Intel owns just over 30 percent of the world
market for flash, followed by Advanced Micro Devices,
Fujitsu, Atmel and Sharp.