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To: D.J.Smyth who wrote (20216)	11/17/1998 5:22:00 PM
From: BillyG	Respond to of 25960

Mitsubishi preps 0.18-micron embedded DRAM process By Anthony Cataldo EE Times (11/17/98, 3:05 p.m. EDT) TOKYO — Mitsubishi Electric Corp. will soon be accepting customers for its 0.18-micron technology, which brings embedded DRAM to new density levels and helps define the company's system-on-a-chip development strategy. With embedded DRAM as the common thread, Mitsubishi is positioning the new process technology for a wide range of consumer, PC and communications applications. Moreover, the company has articulated an integration strategy that stresses the use of more internally developed and third-party intellectual property (IP) cores, and a greater emphasis on CPU-powered middleware. The company has also laid out a more top-down approach to system-on-a-chip design with a new system-modeling strategy. Mitsubishi said it will talk with customers this month and expects to start producing the first devices based on the 0.18-micron technology by next summer. Mitsubishi offers two variations of the process: one, with embedded DRAM integration, runs at a 133-MHz clock speed; another uses integrated SRAM with a slower clock speed but faster logic. HyperDRAM The embedded DRAM version, called HyperDRAM, features a synchronous DRAM core with maximum memory density of 128 Mbits. Mitsubishi has also extended its embedded DRAM I/O capabilities by offering a 512-bit bus in addition to 64-, 128- and 256-bit widths. HyperDRAM has a 6-million-gate maximum. Logic speed is 72 picoseconds. Vcc varies from 1.8 V for the logic portion to 3.3 V for the DRAM portion. The I/O can operate at either voltage. Embedded DRAM, which has seen most of its success so far in graphics chips for portable PC and hard-disk-drive controllers, is attracting more customers, said Manabu Kawashima, a production planning manager for Mitsubishi. Alternatively, Mitsubishi will provide a "middle speed class" 0.18-micron logic process that can include 8 Mbits of embedded SRAM with an I/O bus width ranging from 8 to 128 bits. Because it is based on a pure logic process, it can achieve a maximum density of 8 million gates and has a logic speed of 36 ps. Mitsubishi will offer its library and IP cores for both versions, including its own fully synthesizable embedded M32R CPU. A number of PC interface cores are available, including IrDA, USB, and IEEE 1284 and 1394. Mitsubishi will also offer a number of analog modules, such as phased-locked loops, A/D and D/A converters and bus transceivers. Business model Along with its process technology, Mitsubishi has put in place a business model that pays special attention to application-specific IP, system modeling and the development environment. The goal is to approach system-on-a-chip design from the "bottom" by building an IP library through internal development and outside acquisition, and from the "top" by developing a system-modeling program that integrates various internal bus offerings, an HDL package and a "cycle-accurate" package. With its bus package, for example, Mitsubishi will offer three speeds and even include a fourth bus if a customer has a special request. Mitsubishi's fastest data bus is intended for those cores that need the highest performance, like the CPU. The mid-speed bus, also known as the instruction bus, will link the CPU to peripherals like ROM. The low speed bus handles the interrupt code among peripherals, said Shunsuke Hosomi, manager of Mitsubishi's strategic planning department. Mitsubishi's internal bus scheme supports the bus interface unit (BIU) that was defined by the Virtual Socket Interface alliance to combine multiple buses in one chip. The BIU can be either a common interface attached to cores like ROM, hardware IP, user logic and peripherals, or an interface to connect the main embedded CPU bus to a modularized piece of user logic coupled with DRAM. Mitsubishi's system integration strategy also involves drawing from both internally developed and third-party IP cores and middleware. Mitsubishi will develop unique IP for analog I/F but will turn to de facto industry standards or VSI for CPU peripherals and PC interfaces. Digital signal processing and more application-oriented cores for communications and graphics will be co-developed with customers. At the same time, Mitsubishi is responding to more customer requests to exploit faster embedded CPUs by expanding its middle-ware, Hosomi said. Mitsubishi has broken down system-on-a-chip design software into four categories: software only for the most complex computations and sequential processing; SRAM as a software "absorber" that interfaces to fixed hardware; a mixture of hardware and unfixed software that changes depending on standards being implemented; and a direct hardware/software trade-off scheme, the simplest and least expensive option. To ensure the integrity of system-on-a-chip design that depends more and more on IP, Mitsubishi plans three-tiered IP verification. First, the core is tested in CPU-generated test patterns. Next, a host PC simulator tests it on-chip. Finally, the core is tested in a full system environment. IP verification is one part of a larger development environment for Mitsubishi's system-on-a-chip strategy.