Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (41735)	11/18/1998 12:58:00 AM
From: Steve Porter	Respond to of 1572604

Scumbria, Well when I am writing compute intensive code, I will go as far as counting the cycles of each instruction in my inner loops, and trying to figure out what the CPU is doing with regards to cache management. The problem is that this is very awkward today. I really look forward to the day when cache control is TRIVIAL on x86 and other CPUs and cache monitoring is equally simply.. I also look forward to the day when someone figures out a set of x86 instruction that let me use those "alias" registers naturally. Steve