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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (41768)	11/18/1998 11:31:00 AM
From: Maxwell	Respond to of 1572629

Elmer: <<I can see Intel possibly pulling all cache back on to the die once they get to .18u. They will have reduced design rules for more compact sram cells and at .18u, almost unlimited capacity. The added die area will cost a little more but allow them to maintain a premium price on their highend chips.>> Without local interconnect, Intel cannot maintain small SRAM cell size. Intel 0.18um SRAM cell size is still larger than AMD/IBM/MOT 0.25um SRAM cell size. Unlimited capacity? Now that is all hype. Unlimited = infinity. <<A 600mhz+ Katmai with large on die L2 running with a 133mhz bus + Rambus and AGP4X will command a higher price than a small L2 Celeron on a 66 or 100mhz bus (not to mention blowing away a K7 <g>)>> It is either 133MHz bus or 600MHz Rambus. At 600MHz Rambus the data trnasfer is 1.6GB/sec. At 200MHz SDRAM the transfer rate is also 1.6GB/sec. Rambus is more expensive than SDRAM. This makes 200MHz Alpha/K7 bus more attractive. But in the mean time K7 200MHz is much faster than Intel 133MHz bus. You don't think AMD can make 4X AGP bus? It is not a secret. Maxwell