November 23, 1998, Issue: 1136
Section: News
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Move to 0.18 micron tests AMD
Mark Hachman
Silicon Valley- Just months after Advanced Micro Devices Inc. shook off the ill effects associated with its last manufacturing upgrade, it faces a transition to 0.18-micron process with new resolve.
But AMD claims to have learned from the series of miscues that hindered its transition from 0.35-micron geometries to 0.25-micron.
The company has already successfully completed test runs of wafers processed in 0.18-micron technology at its main production site, Fab 25, in Austin, Texas, according to AMD executives. And it has begun testing wafers based on its forthcoming K7 processor at Fab 30, its newest facility, in Dresden, Germany.
"I tell you, the company has fundamentally changed," said Dana Krelle, vice president of marketing at AMD, Sunnyvale, Calif.
Time will tell. Less than a year ago, AMD's tumultuous transition to 0.25-micron process equipment tipped the chip maker into a sea of red ink; for the fourth quarter of 1997, AMD reported a net loss of $12.33 million on sales of $613.17 million.
During that period, the company was constrained by poor production yields, selling only 1.5 million K6 microprocessors. The primary stumbling block, Krelle said, was not the fact that AMD was forced to swap out older, 0.35-micron equipment for the 0.25-micron lines, but that it could not accomplish the delicate process of reproducing the manufacturing steps used in AMD's R&D fab in Sunnyvale. AMD was forced to develop new methodologies, design rules, and production guidelines, a process Krelle said has been completed.
A year later, AMD's renewed confidence has the company projecting that 4.7 million K6 chips will be shipped in the fourth quarter of this year.
"We're still supply-limited," Krelle said. "But this time, supply is ahead of expectations."
At the fall Comdex exhibition in Las Vegas last week, AMD demonstrated a fully functional 500-MHz K7 processor, accompanied by its two-chip chipset, which incorporates the Irongate north bridge and Cobra south bridge.
Future versions will include 4X AGP connections and IEEE 1394 interfaces, Krelle said. Numerous workstation and server customers had also expressed interest in designing their own chipsets for use in multiprocessor, K7-based systems, he said. The K7 chip that was demonstrated included 512 Kbytes of level 2 cache, and was connected to a motherboard with SDRAM modules mounted on it.
"We don't believe [Direct] RDRAM is going to happen next year," a company spokesman said, adding that AMD has "contingency plans" in place to allow the company to work with both SDRAM and Direct Rambus chips. "We're not very confident in the [production] schedules."
AMD displayed two versions of the K7-one packaged inside a module, like the Pentium II, and another mounted on a printed-circuit board, resembling Intel's Celeron design. AMD does plan a low-cost version of the K7, Krelle said.
Production of the K7 will initially begin at Fab 25. AMD will transition K7 production to Fab 30 by the second half of the year, according to Jack Saltich, vice president and general manager of AMD's Dresden operation. Fab 30's potential capacity is 20,000 8-in. wafer starts per month. By 2000, all of AMD's manufacturing will be on a 0.18-micron process, executives said.
AMD expects Fab 30's first silicon on Jan. 23 on a 0.22-micron process, followed by a quick transition to a 0.18-micron process using copper interconnects, Saltich said. By contrast, Fab 25 will move first to a 0.18-micron process using aluminum interconnects, then to copper-based connections, according to Krelle.
For both companies, the 0.18-micron conversion promises increased performance while lowering power requirements, especially significant in mobile processors.
AMD archrival Intel Corp. is also preparing for its transition to 0.18 micron. At Intel's recent semiannual financial analysts meeting, the company reported that its mobile chips would be the first segment to use the new 0.18-micron process.
"The advent of 0.18 micron should be truly delightful for the mobile user," said Sunlin Chou, vice president and general manager of Intel's Technology and Manufacturing Group, Santa Clara, Calif.
Intel's own manufacturing roadmap is more closely tied to its strategy of reducing manufacturing costs. In wafer starts per week, Intel has planned to commit more capacity to the 0.18-micron equipment currently in development than it did to the 0.25- and 0.35-micron processes already in production, Chou said.
Succeeding process generations fuel higher demand per wafer, which in turn means more capital spending, added Andy Bryant, Intel's chief financial officer, at the meeting.
By diluting the demand for a particular manufacturing process, Intel can lower the associated costs. As an example, the acceleration of the 0.18-micron process-which amortizes the manufacturing cost over a larger number of dice per wafer-reduced Intel's capital-spending budget from more than $5 billion to $4.2 billion, Bryant said.
"The key element here is to concentrate on the cost side as much as we concentrate on the performance side," said Andrew S. Grove, Intel's chairman.
-Additional reporting by Jack Robertson in Munich, Germany, and Jennifer L. Baljko in San Francisco.
Copyright ® 1998 CMP Media Inc.
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