SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Paul Engel who wrote (42133)11/23/1998 5:09:00 PM
From: Kevin K. Spurway  Read Replies (1) | Respond to of 1571699
 
Re: "Is this a new fact or a new position stated by AMD - or just your WAG?"

It's a hypothesis based on the available information (of course there isn't much info available, and what exists is not necessarily accurate):

1) 1/3 speed cache demo'd at Comdex.
2) Expense of producing high speed SRAM's that will work at 300 MHz and beyond.
3) Interview with AMD employees who say there will be no 500 MHz K7.

So I have a question for the technical people out there--what does it take to change the multiplier on the back side bus on the PII? If it's as easy to change as it is for a socket 7 system (i.e. a simple jumper setting) then the speed of the L2 that AMD demo'd at Comdex is irrelevent because it can easily be adjusted. If it's more difficult to make the change (i.e. the silicon must be somehow different--so for example Xeon silicon would be different from PII silicon) then maybe my hypothesis is correct.

Kevin