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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Paul Engel who wrote (42134)	11/23/1998 5:11:00 PM
From: Scumbria	Read Replies (1) \| Respond to of 1571736

Paul, So you are saying that a 1/5 or 1/10 CPU speed backside L2 cache would not be too bad as well? The key issue with an L2 in a single processor system is latency. The terms "full speed", "half speed" and "third speed", used commonly on SI, refer to the number of clocks between beats of data. The only parameter which is of much consequence is the amount of time required to receive the critical (first beat) data. This is a function of the speed of the sram, not the bus speed. Scumbria