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To: MileHigh who wrote (674)	11/23/1998 5:50:00 PM
From: TimeToMakeTheInvs	Respond to of 1225

From the call: See possible 16 new product introductions in qtr.4. Hired 4 new designer this qtr. Showed better product revenue mix, as well as more diversified geographic sales pattern. Expect gross margins to improve, 4rth qtr. rev.s seen up 8-10%, greater R&D spending reflected in many design wins this qtr. which will show in 4rth qtr. sales and especially new customers (several of which are expected to be plus 10% I think - was writing faster than I can read). AR days down to 50, communications 21% of rev., bottom of ATE market seems to have been passed, orders>shipments, turns up as AC mentioned, rev.s up 12%(?) sequentially, see possible 2-5% rev. growth in qtr. 1 and 2 of year 2000 and 5-8% sequential rev. growth in qtr.3 and 4. Cheers everybody. tim

To: MileHigh who wrote (674)	11/23/1998 5:59:00 PM
From: AreWeThereYet	Read Replies (3) \| Respond to of 1225

MileHigh OT Part-2 >> Also, you have to ask yourself (in all sincerity) why would INTC put so much muscle behind RDRAM if it was inferior? << RDRAM's latency problem is discovered when industry is doing real-life testing. It is good in theory (high bandwidth offset the slower latency, high clock-speed offset the fact that it is implemented on a 8bit and 16bit data bus). You may also ask youself (in all sincerity): 1) Why Intel created a cacheless Celeron when all textbooks taught us how crucial is the cache. 2) Why Intel locks the new Celeron A's bus speed to prevent 100Mhz FSB? 3) Why is Intel producing such a low speed Celeron when its fab technology can easily roll out a bunch of 400Mhz Celeron A with 100Mhz FSB? In reality, many power-users are overclocking their Celeron 300A to 450A with 100Mhz FSB without problem! btw: I am not a pro-OC person. 4) Why Intel dropped the cost-effective Socket-7 and Socket-8 design? 5) Why Intel keep the Slot-1 a propreity design? Keep thinking... aC