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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (42149)	11/24/1998 2:21:00 AM
From: Elmer	Respond to of 1571899

Re: "The Mendocino cache is located on chip, and has about 1/2 the latency of the PII cache- which is located on a separate die. Do you remember when I was querying you for details about Mendocino cache latency, early in the year? Now you can see why I was so interested." It could also be 256 bits wide and do the transaction in 1 clock. Or 512 bits wide and do it in 1/2 clock........just kidding.. EP

To: Scumbria who wrote (42149)	11/24/1998 9:20:00 AM
From: Kevin K. Spurway	Read Replies (1) \| Respond to of 1571899

Re: "To paraphrase James Carwell: "It's the latency ......"" Here's a nice editorial from Real World Tech about DRDRAM--some technical issues and some other stuff about a gag rule that the Rambus DRAM imposes on licensees. "Potential problems with the Rambus technology are latency (which is, at the very least, no better than current memory implementations) and power requirements. In fact, many experts seem to agree that for uniprocessor, single user environments, Rambus technology will provide absolutely no benefits whatever! Despite this, consumers will be paying a very hefty price for the privilege of using it." realworldtech.com Kevin