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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Kevin K. Spurway who wrote (42317)	11/28/1998 12:58:00 PM
From: Scumbria	Read Replies (1) \| Respond to of 1572719

Kevin, The performance graphs indicate that memory latency is the bottleneck for Winstone performance. Latency = (# L1 hits * 1 clock) + (# L2 hits * L2 latency) + (# of cache misses * average dram latency). The three key variables affecting this formula are L1 size, L2 size, and L2 latency. The implications from Anand's Winstone graph are: 1. 64K L1 with off chip L2 is sub-optimal (K6-2) 2. 128K onboard L2 is adequate (Celeron A) 3. K6-3 (with 256K onboard L2) will achieve Winstone scores approximately equal to PII, Xeon, and Celeron at the same clock speed. Scumbria