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To: MileHigh who wrote (76)12/5/1998 9:55:00 AM
From: MileHigh  Respond to of 236
 
December 07, 1998, Issue: 1038
Section: News
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IBM samples 256-Mbit parts, joins 10 firms in endorsing format -- DDR picks up steam as next-gen DRAM choice
David Lammers

Santa Clara, Calif. - IBM's Microelectronics Division has started sampling a 256-Mbit double data rate (DDR) synchronous DRAM that will go into volume production in mid-1999 at its fabrication facility in Essonnes, France. IBM also said it will put its muscle behind DDR II, a collaborative effort to develop a memory architecture that will deliver 3.2-Gbyte/second throughput for servers and 9.6-Gbyte/s throughput for point-to-point connections in small systems. DDR II is scheduled to be ready for introduction in 2001.

IBM was among 11 DRAM vendors and large computer manufacturers to voice their collective support for the DDR specification last week, putting the DDR SDRAM back in the race for memory slots alongside the Direct Rambus DRAM (D-RDRAM). After a series of delays, the specifications for the DDR components and 200-pin DDR modules were agreed on this autumn. Only minor issues remain to be resolved for dual-in-line memory modules.

In an important development, companies participating in the Joint Electronic Device Engineering Council (Jedec) committee are buckling down to the task of getting DDR II ready for introduction by 2001. DDR I devices in 64-Mbit densities, which are coming on the market now, and in 256-Mbit densities, which will arrive late next year, operate at 133 MHz at 2.5-V operation. By reading data from the rising and falling edges of the clock, a maximum performance of 266 Mbits/s per pin can be achieved, IBM reported. By improving the electrical interface and moving the frequency to the 266-MHz range, a throughput of 400 Mbits/s per pin is feasible with DDR II.

Steve Przybylski, principal analyst at the Verdande Group, said the work on DDR II "gives the DDR initiative much more credibility, ensuring the server and networking people that this is not just a temporary and partial solution to their memory needs. If you really push the DDR technology," he said, "you can reach the same 1.6-Gbyte/s peak bandwidth performance [as D-RDRAMs], but normally DDR won't be as fast as the Direct Rambus parts on bandwidth."

Though microprocessor vendors Intel, Advanced Micro Devices and Cyrix have endorsed the Rambus architecture for PCs, as has Compaq Computer's server division, Rambus has yet to convince most server manufacturers that the narrow, 16-bit Rambus channel can effectively scale to the multi-gigabyte main memories used in larger servers, analysts said.

Cost is also important, and the DDR components and modules may be less expensive than Rambus memories and modules. All of the additional costs incurred by the Rambus license fee, the requirement for chip-scale packaging and the need for high-speed testers, are multiplied when a high number of the memories are used per system.

Przybylski said server manufacturers typically use a 64-bit memory bus with memory controllers that can control more bits per pin, and in this way can support very large memory configurations. By using switches to control a large number of modules, large system vendors may feel more comfortable with the DDR memories, rather than the "rigidly specified physical configuration used in the Rambus approach," he said.

But once Rambus memories go into volume production, the sheer volumes that may be achieved in the PC sector-which accounts for 60 to 70 percent of all memory bits shipped-could make it difficult for the DDR parts to maintain any cost advantage next year, Przybylski said.

Samples shown

Fujitsu Ltd., Hitachi Ltd. and Mitsubishi Electric Corp. unveiled 64-Mbit DDR DRAMs in October (see Oct. 12, page 37). Last week, NEC Corp. said it was ready to begin sampling a 128-Mbit SDRAM with a CAS latency of 2.5 ns built in a 0.22-micron process.

Bob Merritt, a research analyst at Semico Research (Phoenix), said the support of 11 DRAM and system makers for DDR "is a very significant announce- ment because of what it says, as well as what is not being said. It says that system and PC designers are now assured that one branch of the DRAM family will follow the traditional path of previous high-volume DRAMs. The Jedec vote back at the 64-k DRAM generation established that DRAM manufacturers would focus on lowering component costs by maintaining design simplicity and evolutionary architectural changes. This announcement confirms that adequate support will continue."

Merritt added that "many companies are still concerned about the remaining technical issues and cost forecasts related to the Direct Rambus DRAM architecture." The critical comparison, he said, is not cost per se but "the cost/performance of one DRAM architecture vs. another. This total cost includes the chip set, the connectors, the completed memory module and the support infrastructure. The announcement means that PC manufacturers can directly compare the product availability, cost and performance of more than one architecture, and then select whichever is the most competitive at any given time."

Risk moderated

Lane Mason, a strategist at IBM's memory division, said "because servers use tremendous amounts of memory, any little incremental cost is magnified. Also, the server people are attracted to DDR because of the relative lack of risk in the technology. It leverages the same kind of connectors and modules and packaging that they are used to, so DDR minimizes the technical risk for designs coming to market in 2001 and 2002."

IBM will make a limited number of 64-Mbit DDR SDRAMs, and only for development projects, Mason said. The real thrust will take place with the 0.2-micron 256-Mbit chip that will run at 133 MHz. IBM sent samples of that part to a large external OEM in November. In the future, IBM will apply a 0.175-micron process, and Mason said a 512-Mbit DDR SDRAM "is on our road map." A 128-Mbit version will emerge in late 1999.

Vijay Lund, director of advanced server engineering at IBM, in a statement touted DRR's "reliability features-such as improved error correction-that allow us to build systems with high availability. The efforts of Jedec to define a common DDR specification gives us confidence that we will be able to accommodate future system requirements in performance and capacity in a cost-efficient manner."

Graphics board manufacturers are also likely to adopt the DDR memories, said Victor de Dios, a DRAM market analyst based in Neward, Calif., in part because of DDR's excellent latency and acceptable bandwidth. Many graphics manufacturers compete on price, de Dios said, and some of them will not spend on a Rambus license.

DDR DRAMs could achieve 12 to 17 percent of the total DRAM market by 2001, with as much as half of them going into graphics subsystems and the rest into servers, de Dios said. By late 1999, most higher-density SDRAMs will offer DDR capability as a bonding option, he said.

"Rambus will penetrate at the lower ends of the market," de Dios said. "But for the four-way and eight-way servers, with multiple buses, the timing specifications on the Rambus approach are so tight that it is difficult to design with the Rambus channel."

For the server market, Intel expects that its customers will use both RDRAMs and SDRAMs. AMD recently said that its K7 processor and supporting chip sets will support either synchronous DRAMs or the Direct Rambus memories




To: MileHigh who wrote (76)12/5/1998 9:57:00 AM
From: MileHigh  Read Replies (1) | Respond to of 236
 
December 07, 1998, Issue: 1038
Section: News
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Scheme calls for radical changes to consolidate packaging, assembly and test -- Startup aims to put new spring in wafer test
Brian Fuller

Tokyo - A low-profile probe-card company last week unveiled a new process it claims will consolidate entrenched, time-consuming test and packaging methods, slash costs and bring Moore's Law-type scaling to the back end of semiconductor manufacturing.

FormFactor Inc. (Livermore, Calif.), a closely held startup already involved in wa-fer probe, detailed its Wafer on Wafer (Wow) technology, designed to allow the traditionally separate steps of packaging, assembly and test to be consolidated at the wafer level.

The technique uses so-called Microsprings attached to the wafer for various forms of test and burn-in-before dicing-and ultimately for attachment to a printed-circuit board, according to Jim Healy, vice president of corporate marketing, and a long-time semiconductor equipment hand. The result could be much better control of yield problems on the back end.

The company is targeting memory parts that are cost-sensitive and approaching high volumes, where the efficiencies and cost-savings of the Wow technique can be realized.

Healy does acknowledge challenges ahead in consolidating back-end methodologies, which traditionally are run by different groups. "We're talking about changing an industry, changing an infrastructure. We understand that."

The FormFactor technology is at least a year away in its ideal form, but the company is laying the groundwork to ride the coattails of Rambus DRAMs. In their complexity and expense, those parts are requiring a retooling of test and assembly techniques.

What the company and its founder, Russian emigre Igor Khandros, hope to do is push all test-from pre-burn-in to burn-in to low-speed and high-speed test-to the wafer level. Wafer test is not new, but this technique notably shifts singulation, or dicing, of the wafer from an early step to nearly the last step in the process, eliminating costly steps and extra test handlers and allowing engineers a quicker look into design and fabrication errors, Healy said.

The first step of the process employs a modified bonder to attach tens of thousands of Microspring contacts to the wafer, as are already used in other FormFactor probe products. The springs, made of gold for its electrical characteristics, are plated with nickel alloy to give them spring action. A trace is re-routed from the traditional bonding pad to the springs, which are arrayed on the wafer.

Users can then customize their test methodology, for example starting with wafer-level burn-in and long-cycle test, and then move to a redundancy/repair cycle and so on. After test, the wafer is diced and the contacts are either socketed or soldered to a substrate. The company claims the approach is better than solder balls because it can handle a finer pitch and better than wire bonding because it can maximize pin count. Once placed on the board, the dice can be capped with a heat sink and encased in plastic as well.

The approach allows the IC manufacturer to follows Moore's Law on the back end, which is under threat since test time increases linearly with the number of DRAM bits. Dataquest has reported that the cost model for a 16-Mbit DRAM is $1 per good device on the back end, but vendors are spending nearly five times that on 64-Mbit parts. With Direct Rambus parts ramping, demanding new packaging and expensive test solutions for high-speed performance, Healy and Khandros estimate that back-end costs for the parts could rise by more than 50 percent.

"You never know where the land mines are in something like that but from everything we can gather, it's for real," said Fred Zieber, a market analyst at Pathfinder Research (San Jose, Calif.). "Clearly there's a chicken-and-egg problem in getting it going. You have to have people doing it and people to accept it. It's not an easy deal at all."

Indeed, FormFactor executives don't pooh-pooh the issues of acceptance. While a half-billion dollars in potential revenue has been bandied about as a possible target in a few years, Healy, former president of tester vendor Credence, said he recognizes the entrenched nature of the back-end process. He said that during one customer meeting involving the separate assembly, package and test teams, members from each team, unfamiliar with each other, exchanged business cards and introduced themselves.

Speedy test

Market analyst Dan Hutcheson of VLSI Research Inc. (San Jose) said the Wow approach represents a holy grail in test methodology. "Where this gets interesting for users is to allow them to move speed testing up to probe," he said.

Rather than wait weeks from the beginning of the back-end process until speed test kicks in, the FormFactor process would push it up to days. In that way, a company would avoid sand traps in which thousands of wafer starts, worth say $15 million to $20 million a week, get pushed down the line and engineers don't find out for weeks that they've got 20 to 30 percent yield loss or speed drop, Hutcheson said.

"You can turn yield excursions from weeks to days, you do more cycles of learning in a given production run," he said. "Ideally, you'll get to entitled yields faster. That's not what packaging offers."

Reliability and market acceptance are clearly key to getting the technology off the ground. FormFactor has made one step in the credibility direction by licensing the Wow technology to Shinko Electric Industries Co. Ltd. (Nagano, Japan), a company affiliated with Fujitsu.

"We licensed the Wow technology with the expectation that it will simplify test processes. The more a device becomes high-density and high-speed, the more the test process becomes complicated," said a spokesman of the Japanese company.

Glenn Farris, product manager for high-speed memory test at ATE and memory-test vendor Teradyne (Boston), said there are a host of open issues to be sorted out before Wow can turn heads.

"There are technical issues," he said, "such as can you get all those springs on a wafer and make it work? Then there's the economic factor. In the end, is the overall cost less expensive than traditional packaging and testing?" FormFactor also needs to provide the high-bandwidth interfacing capabilities necessary, for instance, to accommodate a tester like Teradyne's big-iron Aries tester, Farris said. Teradyne is talking with FormFactor and monitoring the process development, he added.

Gary Fleeman, memory product manager at Advantest America (Santa Clara, Calif.), said, "The real benefit of Wow is in reducing the number of times a device is handled, or insertions. Many major companies are desperately trying to cut insertions.

"However," he added, "it's difficult to build a test system that can handle 1,200 die, the number mentioned in FormFactor's Semicon paper. Even so, we still will need multiple inserts because at-speed testing is dramatically different from long-cycle burn-in testing. And a lot of memory suppliers already do a lot of ac speed work on the wafer, although not 128 devices in parallel."

Chip to wafer scale

At the packaging level, many other companies are working on techniques to attach packages while chips are still in wafer form. This heavy development activity has taken off in the past couple of years with the advent of chip-scale packaging (CSP), which adds so little to the IC that it becomes feasible to add packages to a single wafer instead of to many separated chips.

"Wafer scale is a natural extension of chip-scale packaging," said Thomas Di Stefano, a founder of Tessera (San Jose, Calif.), which has licensed its CSP technology to many companies. "One thing that gives it impetus is that wiring normally done on the substrate, like power and ground, can be put in the package, which can reduce the number of I/Os a chip needs."

But the challenges to get wafer-level packaging into production are still high. Tessera has been working on its technique for almost six years, and it's only now shipping parts to IC houses.

FormFactor, as of midyear, had been capitalized to the tune of $13.5 million with backing from Institutional Venture Partners, Mohr Davidow Ventures, Morgan Stanley Venture Partners and Leeway & Co. William Davidow is chairman and the company lists on its advisory board TI's Jack Kilby, Mentor Graphics CEO Wally Rhines, former Intel and now-Dell executive Carl Everett, among others.

It hopes to sell the industry on a Rambus-like business model in which it licenses the technology and process to other companies, such as Shinko. If those companies find compelling cost-savings, and margin advantages for their customers, the process could take off, observers said.

"There's going to be a fair amount of doubt until you get to volume and until reliability gets established," said Pathfinder's Zieber.

But some don't see the process taking hold in the mainstream."I don't think we're going to see chip-scale packaging for three years or so," said Adrian Proctor, general manager of memory-module maker Dane-Elec Corp. (Irvine, Calif.). -Stan Runyon, Terry Costlow and Yoshiko Hara contributed to this report.





To: MileHigh who wrote (76)12/5/1998 10:02:00 AM
From: MileHigh  Read Replies (3) | Respond to of 236
 
Will Direct Rambus Rule the Roost? -- Some DRAM suppliers expect market segmentation.
John H. Mayer

Although it's clear that the next couple of years will see a major shift to new, high-performance DRAM architectures, opinions vary widely on whether the Intel-led Rambus juggernaut will dominate, or the market will be more segmented.

Even if there is some initial segmentation, it can't last long because the market usually swings one way or the other, according to Jim Sogas, director of DRAM marketing at Hitachi Semiconductor (America) Inc., Brisbane, Calif. "But I believe we're going to have definite segmentation over the next couple of years, because we're looking at radically new technologies that are not going to be easy to switch between."

Others, including Bill McClean, president of Scottsdale, Ariz.-based IC Insights Inc., believe that although there may be some segmentation, it won't be as much as some are expecting.

Driving speculation has been the introduction in the past several months of a slew of 64-Mbit double-data-rate (DDR) DRAMs that may be able to give Rambus Inc.'s Direct Rambus devices a run for their money.

In August, Samsung Semiconductor Inc., San Jose, sampled its first 64-Mbit DDR device. In the following two months, Fujitsu Microelectronics, Hitachi Semiconductor, Micron Technology, and Mitsubishi Electronics America introduced a range of DDR DRAMs targeted at high-end workstation, server, and PC applications. Last week, IBM Microelectronics announced shipment of its first 256-Mbit DDR samples. And other suppliers, including Toshiba America Electronic Components and Siemens Semiconductor, plan to announce high-density DDR parts in 1999.

"We have a significant num- ber of customers interested in these parts," said Keith Horn, director of the Memory Marketing Group at Fujitsu Microelectronics Inc., San Jose. Like most of its rivals, Fujitsu is offering 64-bit DDR SDRAMs in x4, x8, and x16 configurations, and plans to sample 128-Mbit devices in the first half of 1999.

DDR's virtues

DDR possesses some technical and economic merits that make it a very attractive solution for next-generation, high-bandwidth systems, according to Lane Mason, director of graphics/memory product strategy at IBM Microelectronics, Burlington, Vt. "The people who are true believers in DDR on the systems side are very strong proponents, have it worked into their roadmaps, and are working with all the vendors to make sure that it is a price/performance success," Mason said.

OEMs find DDR attractive because it offers a significant performance boost without requiring a major architecture shift from SDRAMs.

Boosting performance by transferring data on both edges of the applied clock, DDR offers twice the data rate of conventional SDRAM devices, yet can use the same TSOP package and test equipment.

"The key to [DDR's] popularity is that it represents a very evolutionary path for customers," said Cecil Conkle, assistant vice president of DRAM marketing at Mitsubishi Electronics America Inc., Sunnyvale, Calif.

On the cost side, there's little incremental investment needed to bring DDR to market, vendors say. "It's very easy for DRAM suppliers to produce this part because it's not a major redesign from a synchronous DRAM to a DDR," said Chee Ho, director of marketing at Siemens Semiconductor Inc., Munich, Germany.

The die premium for DDR over single-data-rate SDRAM is 2% or 3%, a negligible difference, Fujitsu's Horn said.

Moreover, memory-IC suppliers have been collaborating to develop the infrastructure needed to make DDR a success. For example, while discussion continues on an eventual 200-pin module, the 184-pin DIMM is now fully specified by JEDEC.

"We've been working to develop a common Gerber tape for the module, and we're working with other infrastructure vendors to push the development of clock drivers and logic as well," Horn said.

But there's still work to be done. "It's a slightly different bus than that used with the SDRAM," said Mike Seibert, marketing manager for DRAMs at Micron Technology Inc., Boise, Idaho. "[DDR] has a reference and a center termination. So we're working with the major customer base and discussing some of the implications of a main memory implementation of DDR where you're putting multiple DIMMs in a system and reviewing how you lay out the busing on a motherboard and what the timing budgets are."

The Intel factor

DDR's biggest obstacle to widespread deployment remains the absence of support from Intel Corp., which has thrown its weight behind the Rambus technology. "Anything can change, but it seems clear Intel will not be leading the parade to the altar of DDR," Mitsubishi's Conkle said.

Still, a number of third-party chipset suppliers are looking at the potential of DDR, according to vendors.

"As an industry group, the DRAM guys are talking to everyone about getting chipset support out there," Micron Technology's Seibert said.

There is currently no commodity chipset that supports DDR, but there are a lot of chipset vendors looking at it, so that may change, according to Kevin Kilbuck, memory applications manager at Toshiba America Electronic Components Inc., Irvine, Calif.

In addition, the absence of support from Intel has little relevance in the high-end server, workstation, and mainframe markets, suppliers point out.

"It's an obstacle for the mainstream PC market, where Intel's chipsets dominate," Fuji-tsu's Horn said. "But it's less of an obstacle at the high end because there the chipset is often a proprietary ASIC-type solution."

Graphics and networking applications also hold significant promise for DDR devices, according to suppliers. "For example, we've spoken to many of the graphics-chipset pro- viders, and the ease of implementation of a DDR interface on their product is a lot simpler than a Direct Rambus," Horn said.

George Iwanyc, an analyst at Dataquest Inc., San Jose, agrees that OEMs in certain markets will find DDR attractive because it offers a significant performance enhancement without forcing a major architectural redesign.

"PC-card vendors and OEMs putting graphics on the motherboard are looking for fairly mainstream memory solutions right now, and workstation and telecom OEMs are still not committed to Rambus," he said. "On the server side, OEMs will want to make sure they're using a highly reliable memory solution, so they probably won't want to go to a leading-edge technology like Rambus until it's well proven. That could offer an opportunity for DDR because it is looked on as an evolutionary change."

Iwanyc expects DDR will represent close to 10% of the DRAM market within the next two years.

Pricing will play a key role in the eventual extent of the DDR market. "As we move forward, the DDR and single-data-rate [SDRAM] parts will be options on the same die, so that gives you some indication that the die cost premium will be minimal," Mitsu- bishi's Conkle said.

Early on, there may be some premium because DDR will be less widely supported and the yields at high speed may not be stellar, but eventually they'll come close to SDRAM's, IBM's Mason said.

Others in the running

A couple of other high-performance DRAM technologies are also competing.

Virtual Channel Memory (VCM), an architecture introduced by NEC Electronics Inc., Santa Clara, Calif., in 1997, boosts performance by modifying the core of the SDRAM and storing data in multiple channels between the input/output buffer and the memory cells. This approach allows the memory chip to prepare other memory data requests in a separate channel while it is reading or writing current data.

For a small silicon overhead and little additional cost, VCM promises a performance boost of up to 25% while extending the life of SDRAM.

Several months ago, NEC and Advanced RISC Machines Ltd., Cambridge, England, announced a joint effort to develop an intelligent memory controller for the new VCM devices for portable computing, multimedia, and embedded applications. In August, JEDEC approved the VCM core technology as an industry standard, and shortly thereafter Siemens announced it would support VCM and provide a second source for NEC's devices.

In addition, three major PC-chipset vendors announced they would develop Socket 7 and Slot 1 PC chipsets to support the technology. But industry support has yet to come close to what exists for Rambus or DDR.

In the meantime, industry momentum appears to be evaporating for SLDRAM, the wideband-protocol, low-cost memory that a number of DRAM suppliers initially supported as a competitor to Direct Rambus.

"We're following the technology, but we have no active design or development work going on there," said Toshiba's Kilbuck, reflecting a view many DRAM suppliers appear to share.

"We're still working on a [SLDRAM] part, but we need someone to drive it from a systems standpoint," Siemens' Ho said. "We can drive it from a component standpoint."

Rambus' availability

If a highly segmented DRAM market does develop over the next several years, it's likely to occur because DRAM suppliers, system OEMs, and Intel failed to meet the plan to deliver Direct Rambus and the infrastructure to support it. Targeted at the massive PC main-memory market, Direct Rambus solutions will represent 5% of the total DRAM market by next year, 30% by 2000, and about 60% by 2001, according to Dataquest.

But if there's any question about availability, that could make everyone think twice, Dataquest's Iwanyc said. "So far, Intel and the Direct Rambus suppliers are hitting all the milestones they've set for themselves," he added.

To help ensure supply of Direct Rambus devices and accelerate their adoption, Santa Clara-based Intel announced in October its plans to purchase a $500 million equity stake in Micron Technology.

"It's really aimed at enabling some production ramp once we have a part," said Jeff Mailloux, DRAM marketing manager at Micron.

While a number of vendors have announced 64/72-Mbit Direct Rambus devices, most are using the lower-density parts to prove the functionality of the technology, while planning mass production of 128-Mbit devices. Micron, for example, is developing a 128/144-Mbit Direct Rambus device that it expects to sample in the first half of 1999. And Samsung was the first supplier to announce, in November, that it had completed development of a 128/144-Mbit Direct Rambus device. Fabricated in a 0.23-micron process, the part supports data rates up to 1.6 Gbytes/s, or roughly 10 times the capability of currently available PC-100 SDRAMs.

Samsung will produce 100,000 devices a month beginning in January, 1999, and plans to boost monthly production to 1 million units by the third quarter of next year.

Vendors credit pricing as much as any other factor for the focus on 128-Mbit devices. "Market prices eroded much faster than anyone wanted them to, making the price gap between a 64-Mbit and a 256-Mbit push out the 256-Mbit time to market," said Avo Kanadjian, vice president of memory marketing at Samsung Semiconductor. "Given that the biggest challenge to driving Rambus demand is making it competitive with SDRAM in terms of price, we're going to take the 128/144-Mbit device to mass production because the relative die-size increase with the Rambus interface will be smaller than on a 64/72-Mbit device," he said.

The expansion problem

Memory-IC suppliers are turning to 128/144-Mbit density for their first volume Direct Rambus devices to address another concern: system expandability. There's a limit to the number of devices a Rambus bus can handle per channel. While OEMs can expand the memory channel by using repeater chips and adding channels to the memory controller, the move to 128-Mbit density for the most part precludes that necessity.

"That was one of the biggest concerns of our OEM customers," Kanadjian said. "With the 64-Mbit generation, you can only support modules up to 128 Mbytes. By going to the 128-Mbit generation, we automatically expanded the module offering from 16 Mbytes to 256 Mbytes, in increments of 16 Mbytes. That's extremely important, because when system manufacturers advertise their systems, they like to specify the range of the memory a user can upgrade to."

The infrastructure for Direct Rambus is quickly falling into place. Smart Modular Technologies has developed Rambus In-Line Memory Modules (RIMMs) in 32-, 64-, and 128-Mbyte densities based on a 64-Mbit Direct RDRAM, and will begin production in the first quarter of next year. Module supplier Kingston Technology is working with Toshiba to bring to market Direct RDRAM RIMMs. And ATE suppliers Hewlett-Packard, Teradyne, and others have rapidly developed high-speed testers for the new technology. At the same time, IC and component suppliers are working on clock generators, memory controllers, and connectors.

Still, no DRAM technology has ever come off without a hitch.

"Even the move from DIPs to SOJs was fairly painful and costly for the industry," Micron Technology's Mailloux said. "Then, in the movement from EDO to SDRAMs, which also meant a movement from SOJs to TSOPs, we went through a period when it was very difficult; and we expect the same kind of challenges for any new technology," he said. "With Rambus, you not only have the high-speed-tester issue, but you're also moving the package from a TSOP to a BGA, which requires all new equipment in the back end."

"In spite of all the activity going on, you don't really get the best check of your technology until you start putting it in the hands of a lot of customers in order to find out how many ways there are to test the true capabilities and tolerances of the part in a wide variety of system operating conditions," Mitsu- bishi's Conkle said. "It's going to be a very challenging environment for manufacturers and users alike."