SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (42711)12/3/1998 5:15:00 PM
From: Scumbria  Respond to of 1578106
 
Ten,

(Write-combining gathers stores to consecutive addresses into cache-line-sized chunks before bursting to the bus.)

This is a feature of minimal value in a single processor system. The vast majority of writes on the bus will be writebacks of dirty data, which are already in cache-line-sized chunks. If the CPU uses a write-allocate cache, there should never be consecutive individual writes appearing on the bus.

Scumbria


HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News