Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : The New QLogic (ANCR) -- Ignore unavailable to you. Want to Upgrade?

To: Craig Stevenson who wrote (19634)	12/4/1998 8:03:00 PM
From: George Dawson	Respond to of 29386

Craig, I noticed it immediately, because I was scanning for features of the MKII. I also wondered about the methodology. For example, the CERN tests did not break it down across the Silkworm ASICs, but the limiting factor in that case was clearly adapter card speed. If there is an ASIC to ASIC latency, I agree that a higher level of integration would be an advantage - especially if adapter latency and throughput becomes less of a factor. George

To: Craig Stevenson who wrote (19634)	12/4/1998 8:22:00 PM
From: George Dawson	Respond to of 29386

Craig, I think this is also a key slide: ncsa.uiuc.edu It is a graphic of storage throughput and CPU utilization under what appears to be realistic conditions. I have confirmed that FC is used only for storage and that the Myrinet network is for messages and that references in the articles to 80MB/s with 11 usec latencies is for Myrinet. The near 90 MB/s is for FC to JBOD storage. This is good news for those of us who have waited for independent verification of Ancor's switch performance. Ideally we will eventually get full details of the exact setup. I would hope to see (like the CERN experiment with the Silkworm) that the MKII is transparent and scales with 100% efficiency. George

To: Craig Stevenson who wrote (19634)	12/4/1998 9:21:00 PM
From: Greg Hull	Read Replies (2) \| Respond to of 29386

Craig, <<Did you note the difference between switch latency on the same ASIC (540ns) versus the switch latency across ASICs (1.7us)?>> <<I realize that it isn't a big deal, but it might indicate that further ASIC integration could keep latencies low.>> My understanding is that the MKII used five ASICs: four 4-port ASICs and one "crossbar" chip. I wonder if the crossbar ASIC accounts for all of the difference in latency, or if other components contribute a significant amount. I was told by Cal Nelson at the annual meeting that a 4 port switch would require only one ASIC, i.e. no crossbar. This would seem to support your assertion that further integration could reduce latency. Greg