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To: D.J.Smyth who wrote (20328)	12/7/1998 10:55:00 AM
From: BillyG	Read Replies (1) \| Respond to of 25960

Players shift seats in quest for 1-Gbit DRAM (the good news is that 1G DRAM requires DUV processing)........... eet.com By Anthony Cataldo EE Times (12/07/98, 10:32 a.m. EDT) TOKYO — The race is on for developing the 1-Gbit DRAM. One of the biggest challenges, say analysts and DRAM executives, will be devising the high-dielectric-constant (high-k) dielectric materials and manufacturing processes needed to simplify the capacitor structure without compromising its ability to store a charge. Major DRAM players are shifting alliances for a better shot at the goal. For one, Fujitsu Ltd. and Toshiba Corp. have forged an agreement to codevelop 1-Gbit DRAMs for 0.13 micron and below-a move that foreshadows an end to Toshiba's alliance with IBM and Siemens and its reliance on trench capacitors. Toshiba and Fujitsu officials said work on 1 Gbit will begin immediately at Toshiba's Advanced Microelectronics Center in Yokohama, Japan. The two companies will assign 100 researchers and spend approximately $250 million on joint development until 2002. The goal is to develop a 1-Gbit DRAM with a chip size of 250 mm2 or smaller, officials said. Meanwhile, Toshiba, IBM Microelectronics and Siemens had been working together on trench-capacitor technology for more than five years. The partnership broke down when Toshiba invited IBM and Siemens to move the work to its research laboratory in Yokohama. IBM and Siemens declined to relocate the research from an IBM facility in East Fishkill, N.Y., according to a Toshiba spokesman. At the same time, a 1-Gbit alliance involving Hitachi Ltd., Mitsubishi Electric Corp. and Texas Instruments Inc. has quietly been dissolved as a result of Micron Technology Inc.'s buyout of TI's DRAM business, officials of those companies said. The shifting alliances have come to the fore as companies scramble to develop a process recipe for 1-Gbit DRAM manufacture at 0.15-micron line widths and below. The move to those ultrafine line widths could come as early as next year and will require vendors to put new generations of materials, lithography tools and photomasks rapidly in place. Brett Hodess, a semiconductor analyst with NationsBanc Montgomery Securities LLC, said at a recent gathering of Semiconductor Equipment and Materials International members here that the number of materials used during a typical semiconductor manufacturing process will double, to 20, as the industry moves from 0.35 micron to 0.13 micron. "We're going to see a lot of new materials hitting at 0.18 micron," he said. "In the past, it was a change in lithography, and not every semiconductor company added the same materials. This is important because with the oversupply situation, most companies are not building new fabs. They will invest in existing plants, and the materials will [determine] which tools will get replaced." "High-density DRAM such as 1-Gbit and 4-Gbit is very different [from preceding generations]," said Masahiro Suzuki, a senior semiconductor analyst with Dataquest Japan. "Companies need lots of money for the development of materials, for example. Thinner [capacitor] oxide is one of the approaches [being explored], but the characteristics of the materials themselves should be different." Indeed, Toshiba and Fujitsu officials said much of the research work will explore high-k dielectric materials that might preserve capacitance levels as the capacitors themselves shrink. Showing the most promise is barium strontium titanate (BST), a ferroelectric material that has been the subject of intense study by major DRAM manufacturers. Both companies acknowledged that they will have to shift from the current trench capacitor used by Toshiba, IBM and Siemens to a stacked-capacitor structure. The length of the subterranean capacitor will have to be extended drastically even as its width narrows to 0.2 micron. The length and thinness of the capacitor make it difficult to fill with high-epsilon materials such as BST, without the materials' glomming together and creating voids, said Toshihiko Ono, senior vice president of Fujitsu's LSI group. The use of BST will come into view this week at the International Electron Devices Meeting in San Francisco, where Mitsubishi will present a paper touting the benefits of using a stacked capacitor with a BST dielectric material for 1-Gbit DRAMs. The company claims to have made progress in incorporating the material into its emerging process technology. While many are pursuing partnerships, others appear comfortable developing DRAM technology on their own. Aside from an informal technology-exchange arrangement with Samsung, NEC Corp. plans to develop its 1-Gbit DRAM technology in-house, a company spokesman said. Mitsubishi is taking a cutting-edge tack in its bid to turn out high-capacity DRAMs. Using a combination of BST and platinum, the company claims it can develop capacitors that can obtain higher capacitance and smaller aspect ratios, require lower processing temperatures and be formed with fewer steps than those built with such other dielectric materials as silicon dioxide and tantalum pentoxide. BST appears to be the first ferroelectric dielectric material that DRAM vendors will embrace. Mitsubishi said it will use BST 0.15-micron to 0.13-micron technology and then will likely shift to PZT (lead zirconate titanate). And Fujitsu and Toshiba will likely use BST for the 0.13-micron generation. Developing the right deposition tool for use with BST is key. "We'll need a smooth step for the covering of BST film, so we're developing BST CVD technology," said Tadashi Nishimura, manager of the advanced device department for Mitsubishi's ULSI development center. "We'll have to work with equipment and gas suppliers." Mitsubishi will also have to come up with a new way to pattern the platinum that is sandwiched between two layers of BST to form the capacitor. New etching techniques will be required for patterning the relatively thick platinum, which will range from 200 to 300 nm in thickness. Mitsubishi has yet to develop a technique for the task, Nishimura said. — Additional reporting by David Lammers.