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Politics : Formerly About Applied Materials -- Ignore unavailable to you. Want to Upgrade?

To: Impristine who wrote (26979)	12/7/1998 10:50:00 AM
From: Jeffrey D	Read Replies (2) \| Respond to of 70976

A little Bear food for you this morning. Jeff << Device Shrinks Increasing Die per Wafer, Eliminating Need for New Fabs -------------------------------------------------------------------------------- PHOENIX (Dec. 7) BUSINESS WIRE -Dec. 7, 1998--A comprehensive analysis of the relationship between semiconductor device shrinks and overcapacity and the effect on semiconductor equipment industry was released by Semico Research Corp. The analysis concludes that the economic recovery of the industry will not occur in earnest until 2000, following the semiconductor manufacturing recovery by 4 or more quarters. With shrinks of the DRAM memory cell, possible die per wafer value is doubling at an ever-increasing rate. Cell size area reduction is enabled by equipment and process technology improvements. When the industry was at 0.35 micron design rules and a cell size of 1.75mm, a wafer could produce 100 64Mb die per wafer. Just prior to 0.25 micron design rules, cell area decreased to 0.95mm and allowed 200 die per wafer. Recently, cell areas on 64Mb devices were estimated at 0.50mm producing more than 400 die per wafer. From a manufacturing perspective this trend is required for survival, but as a result is effectively creating the equivalent of another $1.5B factory every time a doubling of die per wafer occurs. For every fab not built, semiconductor equipment lost revenues can be measured in the hundreds of millions-dollars range. This is illustrated by the SEMI book-to-bill ratio currently at 0.56:1. Microprocessors as measured by transistors per area follow a trend similar to that of DRAM; however, the trend is less pronounced but nonetheless prevalent when plotted as devices per wafers. The result is still the same -- no factories are being built. Equipment segments exhibiting the highest growth until recovery will be predominately enabling technologies closely tied to sub 0.25 micron lithography and advanced processing of transistor or interconnect segments of semiconductor devices. In addition to lithography, enabling technologies include tools which allow advanced CVD and alternative spin-on techniques, chemical mechanical planarization (CMP), rapid thermal processing (RTP), and high aspect ratio etch. Capacity purchase of capital equipment will not resume until semiconductor companies return to profitability. For a copy of this report or other services available at Semico Research visit www.SEMICO.COM Semico Research Corp. is a leader in providing semiconductor market analysis, research and custom consulting. Its headquarters are in Phoenix, with offices in northern California and Boston, as well as Europe and Japan. >>