Intel Investors - Intel's IEDM Paper on their 0.18 Micron Process is provided below - Copyright IEEE and Intel Corp.
The process uses 6 layers of metal (aluminum alloy-based) and fluorinated SiO2 for reduced dielectric constant.
Gate lengths are 0.14 micron PRINTED.
Source-Drain regions - and poly gates - are silicided - TiSi - for reduced sheet resistance.
Note that the 16 Megabit DRAM test vehicle (207 sq. mm.) runs at over 900 MHz at only 1.5 volts !
Graphics figures are omitted but the "captions" are included - sorry, but that's the way it goes in Text-Based SI space.
Paul
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A High Performance 180 nm Generation Logic Technology
S. Yang, S. Ahmed, B. Arcot, R. Arghavani, P. Bai, S. Chambers, P. Charvat, R. Cotner, R. Gasser, T. Ghani, M. Hussein, C. Jan, C. Kardas, J. Maiz # , P. McGregor, B. McIntyre, P. Nguyen,
P. Packan * , I. Post, S. Sivakumar, J. Steigerwald, M. Taylor, B. Tufts, S. Tyagi, M. Bohr
Portland Technology Development, * TCAD, # QRE, Intel Corporation, Hillsboro, OR 97124
Abstract
A 180 nm generation logic technology has been developed with high performance 140 nm LGATE transistors, six layers of aluminum interconnects and low-e SiOF dielectrics. The transistors are optimized for a reduced 1.3-1. 5 V operation to provide high performance and low power. The interconnects feature high aspect ratio metal lines for low resistance and fluorine doped SiO2 inter-level
dielectrics for reduced capacitance. 16 Mbit SRAMs with a
5.59 mm 2 6-T cell size have been built on this technology as
a yield and reliability test vehicle.
Introduction
Advanced logic technologies now lead the industry in
requirements for transistor performance, interconnects and
lithographic resolution. Transistor performance still
dominates overall microprocessor speed and aggressive gate
oxide and gate length scaling are needed to meet
performance requirements. Power consumption is a
growing consideration for microprocessors and continued
supply voltage scaling is needed to meet power
requirements. High performance microprocessors are also
placing greater demands on interconnects. Interconnect
density requirements can be met by scaling pitch and
adding additional layers. Interconnect performance and
power needs can be met by using mature aluminum
technology with high aspect ratio metal lines for low
resistance and low-e dielectrics for reduced capacitance.
Increases in the amount of on-die cache memory on
microprocessors is increasing the demand for small memory
cells while not compromising the performance of logic
circuits.
Transistors
Figure 1 illustrates the structure of the MOS
transistors and isolations used in this technology. The
transistor process flow starts with P-/P+ epitaxial silicon
wafers followed by the formation of shallow trench
isolation. N-wells are formed with deep phosphorous and
shallow arsenic implants, while P-wells are formed with
boron implants. The trench isolation is 530 nm deep to
provide good intra- and inter-well isolation. The minimum
N+ to P+ spacing is conservatively set at 560 nm, as
demonstrated in Figure 2. Latchup is not observed even at
spacings less than 560 nm due to the optimized well and
trench structure and low 1.5 V supply voltage. The
electrical gate oxide thickness is 3.0 nm as measured at 1.5
V under inversion conditions. As shown in Figure 3, the
dielectric time to fail of the 3.0 nm gate oxide exceeds the
requirement for 1.5V operation with allowed tolerances.
Complementary-doped polysilicon is used to form surface-channel
N-MOSFETs and P-MOSFETs. DUV lithography
is used to pattern the polysilicon gate layer down to LGATE
dimensions of ~140 nm. Shallow source-drain extension
regions are formed with arsenic for NMOS and boron for
PMOS. Halo implants (boron and arsenic) are used in both
cases for improved short channel characteristics. Low N+
and P+ junction capacitance values of 0.65 and 0.95 fF/mm
2
at 0 V are provided to improve performance and reduce
active power. Sidewall spacers are formed with CVD Si3N4
deposition followed by etchback. TiSi2 is selectively formed
on polysilicon and source-drain regions with a nominal
sheet resistance of 3 W/sq. Worse case sheet resistance of 5
W/sq is maintained for poly-Si line widths down to 110 nm
as shown in Figure 4 for poly-Si lines with alternating N+
and P+ doping.
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===========Graphics Missing - Of Course !============
N+ N+
N+
P+ P+
P+
N-well P-well
TiSi 2 Si 3 N 4
STI
Fig. 1 Schematic cross-section of transistors
0
5
10
15
20
-400 -300 -200 -100 0 100 200 300 400
Spacing (nm)
P+/PW N+/NW
and N+/Nwell isolation
{===============================================}
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+8
5 67 89101112
E (MV/cm)
TDDB (sec)
Capacitor data
SRAM data
Worse
Case
Field
Fig. 3 3.0 nm gate oxide TDDB at 125C
0
1
2
3
4
5
6
7
8
100 120 140 160 180 200
LGATE (nm)
Sheet Rho (ohm/ sq)
N+/P+ Polysilicon
Fig. 4 TiSi2 sheet resistance vs. polysilicon line width
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MOSFET short channel characteristics are well
controlled down to physical gate lengths (LGATE) of 130 nm
for NMOS and 150 nm for PMOS due to the use of a thin
3.0 nm gate oxide and careful optimization of source-drain
extensions and halo implants. Saturation drive currents at
1.5 V are 0.94 mA/mm for NMOS and 0.42 mA/mm for
PMOS at these LGATE targets (Figure 5). Saturation
transconductances are 860 and 430 mS/mm for NMOS and
PMOS devices respectively. Subthreshold slopes for both
NMOS and PMOS devices are less than 90 mV/decade at
an IOFF value of 3 nA/mm (Figure 6). Short channel
threshold voltage roll-off characteristics are shown in
Figures 7 and 8. Threshold voltages at 1.5 V drain bias are
0.30 V for NMOS at 130 nm LGATE and -0.24 V for PMOS
at 150 nm LGATE. NMOS and PMOS drive current vs. off
current characteristics are shown in Figure 9. These results
are better than any previously published bulk [1-3] or SOI
[4-5] devices. Figure 10 shows inverter gate delay vs. gate
length for unloaded ring oscillators (fan out = 1) operating
at 1.3 V and 1.5 V and at room temperature. The delay per
stage at minimum gate lengths is <13 psec at 1.3 V and <11
psec at 1.5 V. These fast delays are obtained even with a
conservative IOFF value of 3 nA/mm.
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=============Graphics Missing ===========
0.0
0.2
0.4
0.6
0.8
1.0
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
VDS (V)
m)
PMOS
LG = 150 nm 1.5V
1.2V
0.9V
VGS = 0.6V
LG = 130 nm
NMOS
Fig. 5 MOSFET I-V curves
1E-12
1E-10
1E-08
1E-06
1E-04
1E-02
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
VGS (V)
VDS = 1.5V
VDS = 0.05V
PMOS
LG = 150 nm LG = 130 nm
NMOS
Fig. 6 MOSFET subthreshold curves
0.0
0.1
0.2
0.3
0.4
0.5
50 100 150 200 250 300
LGATE (nm)
V (V) VDS = 1.5V
VDS = 0.05V
Fig. 7 NMOS threshold voltage vs. gate length
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
50 100 150 200 250 300
LGATE (nm)
V (V)
VDS = -1.5V
VDS = -0.05V
8 PMOS threshold voltage vs. gate length
1998 IEEE
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Six metal layers are used to address the increasing
importance of interconnects to microprocessor performance
and density. Contacts and vias are all filled with tungsten
plugs formed with PVD Ti/CVD TiN adhesion layers and
blanket tungsten deposition followed by chemical-mechanical
polish. The metal stack is Ti/Al-Cu/Ti/TiN
which provides low line resistance, good electromigration
and low via resistance. The pitches and thicknesses of the
interconnect layers are summarized in Table 1. Aggressive
metal aspect ratios (thickness/width) are used to provide
low interconnect resistance at tight pitches. Figure 11
summarizes a study that compares the metal sheet
resistance vs. pitch for this technology to Intel's previous
0.25 mm technology [6] and to a recent copper interconnect
technology [7]. For a given pitch, this aluminum
technology has a lower sheet rho than any reported to date.
M1 pitch is tight for optimal density as a local interconnect
and for a small 6-T SRAM cell size. M2 and M3 use an
intermediate pitch to optimize both density and
performance. M4, M5 and M6 use increased pitches and
thicknesses to optimize for low resistance and for fast
signal propagation. The process uses a total of 21 masking
layers, combining DUV for critical layers and I-line for
non-critical layers.
Sheet Rho (mohm/ sq)
The inter-level dielectric between polysilicon and
metal 1 is PSG planarized by chemical-mechanical polish.
The inter-level dielectric between the metal layers is HDP
oxide doped with 5.5% fluorine and planarized by
chemical-mechanical polish. Fluorine is added to SiO2 to
reduce dielectric constant and improve interconnect
performance [8, 9]. The use of SiOF as an inter-level
dielectric reduces the dielectric constant to 3.55 compared
to 4.10 for undoped HDP and PTEOS oxides. Metal
interconnect intensive ring oscillators were used to quantify
the speed benefit of SiOF ILD. A M2/M3/M4 sandwich
structure with interdigitated M3 lines sandwiched between
planes of M2 and M4 was used to test total M3 line
capacitance. A M3 isolated structure with interdigitated
M3 lines and no M2 or M4 planes was used to test lateral
M3-M3 line capacitance. As shown in Table 2, ring
oscillator frequencies showed an increase of 16% for the
sandwich structure and 14% for the isolated structure with
the use of SiOF. The fact that SiOF improves the
performance of both isolated and sandwich structures
indicates that it is effective in improving both in-plane and
out-of-plane capacitance. The ILD capacitance reduction is
important for both improving interconnect performance and
for reducing chip active power. A cross-section of the
interconnects used on this process is shown in Figure 12.
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Dielectric M2/M3/M4 M3
Constant Sandwich Isolated
HDP SiO2 4.10 -- --
PTEOS 4.10 +0% +5%
HDP SiOF 3.55 +16% +14%
e RO incr. RO incr.
Table 2 ILD effects on e and ring oscillator frequency
M6
M5
M4
M3
M2
M1
Fig. 12 Process cross-section
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16 Mbit SRAM
A 16 Mbit CMOS SRAM has been designed and
fabricated on this technology with high yields. This SRAM
is used as a yield and reliability test vehicle during process
development and to test and refine the SRAM cell and
support circuitry to be used in logic products. A 6-T
memory cell is used with dimensions of 2.22 x 2.52 mm and
an area of 5.59 mm^2. Figure 13 shows top views of the cell
after polysilicon and metal 1 layer processing. Three layers
of metal are needed to make the SRAM cell functional: M1
for internal hook-ups and VDD strapping, M2 for bitlines
and VSS strapping, and M3 for wordline strapping. M4,
M5 and M6 are added to the cell as redundant VDD, VSS and
wordline straps to make the 16 Mbit SRAM an appropriate
process development vehicle for a 6-layer logic technology.
The 16 Mbit SRAM die size is 207 mm 2 and a die photo is
shown in Figure 14. The SRAM operates at >900 MHz at
1.5 V.
Fig. 13 5.59 mm
2 6-T SRAM cell at poly gate layer (left)
and metal 1 (right)
Fig. 14 16 Mbit SRAM die photo, 14.25 x 14.55 mm
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Conclusion
A 180 nm generation logic technology has been
developed and demonstrated with high performance,
reduced power transistors. Aluminum interconnects with
low-e SiOF dielectrics are used to meet interconnect density
and performance requirements. The technology yield and
performance capabilities have been demonstrated on a 16
Mbit SRAM which operates at >900 MHz..
Acknowledgment
The authors would like to acknowledge the hundreds
of people in Intel who contributed to this technology
development effort.
References
[1] M. Rodder, et al., IEDM Tech. Digest (1997) p. 223.
[2] I. Yang, et al., Symposium VLSI Technology (1998) p. 148.
[3] L. Su, et al., Symposium VLSI Technology (1996) p. 12.
[4] F. Assaderaghi, et al., IEDM Tech. Digest (1997) p. 415.
[5] D. Schepis, et al., IEDM Tech. Digest (1997) p. 587.
[6] M. Bohr, et al., IEDM Tech. Digest (1996) p. 847.
[7] D. Edelstein, et al., IEDM Tech. Digest (1997) p. 773.
[8] H. Oyamatsu, et al., IEDM Tech. Digest (1995) p. 705.
[9] G. Lucovsky and H. Yang, Mat. Res. Soc. Symp. Proc., vol.
443 (1997) p. 111. |
