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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: TGPTNDR who wrote (69670)	12/9/1998 7:25:00 PM
From: Joey Smith	Respond to of 186894

All: Article on Intel's .18m process technology. Looks like Intel will be 1999's semiconductor manufacturing leader, hands-down! joey eet.com Home Headlines Careers Columns IP Watch Intel sticks with aluminum at 0.18 microns By David Lammers EE Times (12/09/98, 4:56 p.m. EDT) SAN FRANSISCO — Intel Corp. came to the 44th International Electron Devices Meeting with a description of the 0.18-micron process it will take into volume production next year with its Katmai processor. The delay per stage was reported to be less than 11 picoseconds at 1.5 V, which Intel claims is the best reported in the literature to date for a 0.18-micron process. The process was designed for operating voltages of 1.3 to 1.5 volts. And instead of using copper, the company is sticking wiht aluminum wiring, for now. Eschewing copper, Intel chose to stick with aluminum wiring, but adopted a fluorided silicon oxide (SiO2F) material for the inter-level-dielectric. By adding 5.5 percent fluoride to silicon dioxide, the ILD has a k value of 3.55, compared with 4.1 for Intel's previous SiO2-based ILD. By using the lower-k dielectric, and pushing the aspect ratio (height vs. width) of the metal lines to reduce the resistance of the narrowly spaced lines, Intel claims that its 0.18-micron technology is faster than IBM Corp.'s copper-based process, and at lower process costs. A test-vehicle chip created with the process-a 16-Mbit SRAM with more than 100 million transistors-operates at 900 MHz. The SRAM cell takes up 5.9 square microns per six-transistor cell, an indicator of the area required to eventually put large amounts of cache on the same die as the processing core. The 0.18-micron process "is poised to go into volume production in the next few quarters," said Simon Yang, the Intel engineer who presented the paper at IEDM. The Intel process-development group was able to achieve a 130-nm physical gate length for the NMOS device, and 150 nm for the PMOS transistors. Intel has gone to more aggressive gate-length scaling. Mark Bohr, director of process architecture and integration at Intel's site at Hillsboro, Ore., said that at the 0.35-micron technology node the gate length also was 0.35 micron; at the 0.25-micron generation (as defined by the Semiconductor Industry Association's road map), the gate length was "close to 0.2," and in the 0.18-micron generation the gate length was scaled to 0.13 micron. Rather than shift to copper interconnects and a dual-damascene process, Intel chose to put its energies into figuring out how to create the "tall and skinny" wires that can be spaced far enough apart to avoid capacitive coupling, and yet with enough metal to reduce the resistance that plagues thin wires. Switch coming Bohr said IBM adopted copper but did not achieve the 2:1 aspect ratio. "There is no question that copper is a good technology. At some time in the future-perhaps at 0.13 micron, certainly at 0.1 micron-we will switch to copper," he said. "The demands placed on the interconnect increase with each generation, and as we scale the interconnects [to smaller dimensions] the resistance increases, so we will need copper." Copper is a more expensive technology, and the benefits at 0.18-micron line widths are not compelling, Bohr said. The same cost-vs.-performance argument pertains to silicon on insulator (SOI). "I have not seen the data, even from IBM, that shows a performance advantage in going to SOI," said Bohr. There is a paper [from IBM] at this conference that has a 10-ps stage delay with an 80-nm gate. We achieved an 11-ps stage delay with a 130-nm gate today, in a process that is shippable next year." Bohr said the SiO2F material used for the ILD dielectric is relatively easy to work with because it does not require an additional nitride layer above the substrate. While the adhesion property of the SiO2F material is not as good as silicon dioxide, the performance improvements were worth the material change, he added. The process requires 21 mask layers, slightly less than half of which need deep-UV lithography. The other mask layers use I-line lithography. Intel scaled the gate oxide down to an effective electrical thickness of 3 nm, meaning that the gate oxide has an insulating value equivalent to a 3-nm layer of pure SiO2. Bohr said that gate-oxide scaling "is more aggressive than anyone else is doing." Lucent Technologies has said it will use a 2.7-nm gate oxide in its 0.18-micron process, but that technology will not go into volume manufacturing until well after Intel is in production, he said. With 6 megavolts/cm2 passing through the gate oxide, Intel's reliability tests indicate that acceptable failure rates after 10 years of operation can be assured at the 3-nm gate-oxide dimension, Yang said.