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To: FJB who wrote (1684)	12/10/1998 5:28:00 PM
From: Artslaw	Read Replies (1) \| Respond to of 3813

Robert, Just one quick comment. I don't follow Intel's processing too closely (they don't talk much about it anyway), but I'm pretty sure that if they say they have a 0.18µ process, they don't have 0.13µ physical gates. They might have 0.13&mu effective channel lengths (the distance the electrons (in nMOS) have to travel from one side of the transistor to the other). This is because (among other things) the source and drain (the contacts on either side of the channel) undercut the gate. This is usually on purpose now since they have a shallow 'tip' region, but in the old days more due to uncontrollable lateral diffusion. As far as Intel switching to a damascene approach for copper to save a step, Intel had another talk at IEDM entitled "Copy Exactly!" Their thesis was to use the same processing flow for the same technology without exception. This is a well-known Intel trait, but they had some figures to really back up the advantages (essentially new fabs immediately benefited from yield improvements on the developmental line). Intel also recently bragged about their high re-use of equipment. For these reasons, I wouldn't expect Intel to throw away all that they have learned about Al interconnect to try dual damascene--yield reduction and new equipment might be far more expensive. I also don't know if Al actually works for damascene. As it is, most people use tungsten plugs to connect one Al metal layer to another (damascence inherently uses the same metal as the interconnect lines), so there may be a processing reason preventing Al damascene. Regards, Steve