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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Cirruslvr who wrote (43314)	12/14/1998 12:54:00 AM
From: Paul Engel	Read Replies (2) \| Respond to of 1573198

Cringe - Re: " Do you know how good Intel's .25 process is compared to AMD's considering that AMD will producing a 450MHz processor next quarter, albeit a few months after Intel's. " Intel's process is much more robust - 450 MHz Pentium II's are in plentiful supply - every OEM has them and sells them - Gateway and Dell and Compaq and IBM run adds all day long on CNBC and on the NFL games on Sunday advertisingn these machines. AMD seems only able to provide a small number of 400 MHz K6-2's to Compaq and NO OTHER MAJOR OEMs. Re: " Can an efficient design of the processor itself enable higher clock speeds or is it soley based on the process the processor is manufactured on?" The design/architecture and the process are intertwined in determining ultimate CPU speed. Paul

To: Cirruslvr who wrote (43314)	12/14/1998 1:05:00 AM
From: Yousef	Respond to of 1573198

Cirruslvr, Re: "Can an efficient design of the processor itself enable higher clock speeds or is it soley based on the process the processor is manufactured on? (Maybe Tech, or Yousef can answer that one)" I would be happy to give you my thoughts ... It takes both a good/efficient design AND a high performance IC process to enable high clock speeds. So since AMD is having such a hard time getting above 400mhz, I wonder which element is lacking ... Is it poor design OR inferior IC process ?? Did you just "cringe", Cringe ?? <ggg> Make It So, Yousef

To: Cirruslvr who wrote (43314)	12/14/1998 1:46:00 AM
From: Ali Chen	Respond to of 1573198

<Can an efficient design of the processor itself enable higher clock speeds or...> It is not a matter of simple "efficiency" of a design, but rather a matter of the whole design philosophy. DEC has invented the idea of "short tick design" where every step in instruction/data handling is greatly simplified, and therefore requires less CMOS gates (in sequence) to perform the logical functions. This makes the processor to soar in frequency. However, the amount of logical operations that needs to be performed per each insruction remains the same, so the number of steps in processor pipeline must be increased, and the processor effectively can execute less instructions per clock. So, there is some balance. Intel got this idea from DEC and designed the PPro/P-II. AMD and Cyrix were not exposed to the DEC's revolutionaly approach. They took somewhat older approach and designed chips for maximum instruction rate per clock. The processor pipeline in K6/Cyrix is made fairly short - an instruction gets executed in 5-6 clocks compared to 12-14 for P-II. The trick is that in this approach each logical block become too complicated and must contain many sequential gates per their pipeline stages, simply because the amount of logical work is roughly the same for the same set of instructions. The signals have to propagate sequentially through these sequential gates in each stage until latched by next clock in the next stage, and this delay becomes proportionally longer than for the "short tick" design (where the number of sequential gates is strictly limited). As we know, despite the differences in maximum operating frequency, both approaches yield approximately the same results when embedded into similar memory environment (Cyrix 233MHz with inferior memory/cache bus performs roughly equally to 300Mhz P-II). Now look. Recently the Intelafons bragged here about their FET delay in 0.18 Intel technology as 10 picoseconds. If that "Make It So" idiot is right and the speed of a microprocessor is solely determined by how good the FETs are, the Katmai would run at 100 GHz!!! (10ps = 1/100GHz). It is NOT. Now derive your own answer to your question whether "is it soley based on the process the processor is manufactured on". The origin of the K7 team leader may be a hint:) - Ali