To: Joey Smith who wrote (69914 ) 12/17/1998 10:40:00 AM From: Tony Viola Respond to of 186894
Joey and Intel investors, here's an article about copper vs. aluminum chip interconnects that explains some differences at a level not requiring a PHD. It's by Katherine Derbyshire, who is Managing Editor of Semiconductor Online and a frequent contributor to the AMAT thread. Thanks to Katherine. Remember that Intel is staying with aluminum for 0.18 micron.news.semiconductoronline.com T O D A Y ' S N E W S A N D A N A L Y S I S... IEDM Reviews Interconnect Tradeoffs Resistance of a line increases as its cross section decreases. Therefore, as interconnect lines shrink, circuit delays increase. In theory, lower resistivity metals like copper allow designers to maintain circuit performance at smaller design rules. In practice, the situation is more complicated. Copper integration schemes use high dielectric constant materials like Si3N4 as etch stop and barrier layers. As M. Igarashi and coworkers at Mitsubishi Electric Corp. (Hyogo, Japan) explained Wednesday at the IEEE International Electron Device Meeting (San Francisco, CA), etch stop layers significantly increase parasitic capacitance, and therefore the circuit delay. The Mitsubishi group compared total delay for three different wiring schemes. The first scheme used Al interconnects with tungsten (W) plugs for contacts and vias. The second scheme used dual damascene Cu wiring, holding the metal thickness constant (i.e. the same thickness as in the Al scheme). The third scheme also used dual damascene Cu wiring, but held the metal resistance constant. The k value of the dielectric layers varied from 4.0 (SiO2) to 3.0 (SiOF). When the metal thickness was held constant, Igarashi said, the resistance of Cu wire was about 30% less than that of Al wire, in agreement with previous results. However, the parasitic capacitance of the Cu scheme was larger. For fine metal pitch lines (0.30 µm) shorter than 3mm, Al wiring had smaller RC delays than either Cu wiring scheme. For short distance wiring, such as wiring within a circuit block, capacitance reduction appears to have a greater effect on speed than resistance reduction. The advantages of copper were visible in coarse pitch lines (0.70 µm), where both Cu wiring schemes had smaller circuit delays than the Al wiring scheme. The advantage of Cu was smaller when low-k dielectrics were used. Resistance improvements appear to be more effective in long distance wiring, such as between circuit blocks. Based on these results, the Mitsubishi group used Al interconnects for the first four metal layers in an 0.18 µm device, with Cu interconnects for the two upper metal layers. Circuit delay is the product of resistance and capacitance, and therefore decreases when either of those values decreases. Crosstalk, in contrast, as G. Lecarval and coworkers from the LETI research institute (Grenoble, France) explained, depends on the ratio of the line-to-line coupling capacitance to the total capacitance. As such, crosstalk increases as line pitch decreases, but is relatively insensitive to materials. In simulations, Cu wiring had the same crosstalk performance with the ideal dielectric, air (k=1), as with low-k dielectrics (k=3). Al wiring with low-k dielectrics gave the best crosstalk performance. In general, Lecarval said, crosstalk and circuit delay have opposite responses. Delay decreases as metal thickness increases, while crosstalk increases. This behavior will force a design tradeoff between circuit delay and signal integrity. A Tuesday evening panel discussion titled, "Do copper and low-k solve all our interconnect related problems" was cancelled when a power outage forced schedule changes. These results suggest that the answer to the question would have been an emphatic "No." Copper and low-k dielectrics give designers more weapons, but do not end their battle for maximum performance. By Katherine Derbyshire