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Technology Stocks : Xilinx (XLNX) -- Ignore unavailable to you. Want to Upgrade?

To: Skeeter Bug who wrote (2159)	12/29/1998 6:30:00 AM
From: Bilow	Read Replies (1) \| Respond to of 3291

Hi Skeeter Bug; Those links showing memory companies going into logic sure looks like competition to me. I sure miss those sweet Altera tools, particularly the schematic capture... The Virtex series has some (undoubtedly temporary) problems with its tool set. First of all, the "Logiblox" are almost not at all supported. What are those, you ask? They are probably the one thing that has speeded up engineering productivity in FPGAs since 10 years ago. A Logiblok is a pile of logic that is parameterizable. Typical parameters specify how wide the part is. That is, how many bits a counter has, or how large a number an adder can add. Other parameters specify the function that the logic performs, choosing subtraction instead of addition, for instance. Altera has a somewhat easier to use (of course) equivalent, but they are called, more or less, LPMs, and I forget what that stands for. With both companies, the logic is reasonably optimized for the FPGA. Without parameterizable logic, I have been forced into using the ancient techniques of FPGA logic design. Everything has to be defined in terms of "primitives", which, if you want to get decent performance, are at the flip-flop or XOR gate level. There are Xilinx supplied "macros" that are more complicated, (for instance 16-bit adders) but using high-level macros prevents you from utilizing some of the new features of Virtex, in particular, doing cool things with the carry chains and the "MULT_ADD" primitive. There is another complication in the Virtex part that Xilinx needs to resolve and that is the "RLOC" attribute as it applies to Virtex. RLOC is how you specify to the "mapper" what the relative location of those parts of your logic that are either extraordinarily critical, or are repetitive and take up lots of space. Basically, you tell the mapper to place this flip-flop "two rows lower, and one column to the right" of some reference location. The complication arises in a thing called the "slice". The old Xilinx 4000 series configurable logic block, (or CLB) had two more or less independent functions each. They were distinguished by "F" and "G" designations, and they formed two bits in the carry chains. The new CLBs have four functions, comprising two bits in two separate carry chains. The two carry chains are distinguished by a slice designation, either ".S0" for the first slice, or ".S1" for the second slice. Each slice has two function generators (i.e. look up tables or LUTs), but I don't think you can address them individually. The problem is that when you specify an RLOC for a flip-flop, you must specify the slice. You have to decide what slice your logic is going to have to go into at the time you design it, or, alternatively, you have to create two copies of it, one for each slice. This is really ugly. As an example, the standard 16-bit adder macro supplied by Xilinx is locked to slice "1". If you want to put two adders in a single column of CLBs, you will have to make your own macro, the standard one doesn't do that. The other problem has to do with the new carry chains, and how they interact with the mapping software. But I'll post that in the next message. -- Carl (I'm hoping some of this gets back to the XLNX system programmers. I know you're watching your stock price, guys! Improve the tools, and kick you know who's you know what!)