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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Craig Freeman who wrote (44202)	12/28/1998 11:25:00 PM
From: Tenchusatsu	Respond to of 1572460

<How much L2 is actually screened onto CeleronA silicon? I know that we only get to see 128K but does Intel provide some remapable cells to increase yield? Same question re: the K6-3.> Yep, it's probable that the Mendocino's L2 cache has redundant columns to take care of any defect in the cache part of the die. How much is uncertain. I'm almost positive that AMD would be doing the same thing with the K6-3. This way, you can increase the die size without impacting yield that much. Tenchusatsu

To: Craig Freeman who wrote (44202)	12/29/1998 12:01:00 AM
From: Paul Engel	Read Replies (1) \| Respond to of 1572460

Craig - Re: " How much L2 is actually screened onto CeleronA silicon? I know that we only get to see 128K but does Intel provide some remapable cells to increase yield? " What you are referring to is REDUNDANCY - the addition of extra memory cells to replace non-functional memory cells within the basic 128 KiloByte array. Intel does allow for redundancy, incorporating both extra COLUMNS and ROWS of memory cells. A row or column, with one or more bad SRAM cells, is replaced by A SPARE (REDUNDant) ROW OR COLUMN, assuming these spare units are defect free. I'm not sure how the 128 K is laid out, but typical redundancy levels would be 4 extra columns and 4 extra rows. Paul