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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Bill Jackson who wrote (44254)	12/29/1998 4:31:00 PM
From: Pravin Kamdar	Read Replies (1) \| Respond to of 1572776

K6-3 review: sharkyextreme.com Pravin.

To: Bill Jackson who wrote (44254)	12/29/1998 4:48:00 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 1572776

<Can you intermix risc instructions in with x86 instructions and have those ones bypass decoding and go directly to the execution unit?> Unless I'm mistaken, I think that's what an instruction trace cache is for. Instead of storing undecoded x86 instructions in half of the L1 cache (e.g. Pentium, P6, K6), you store the instructions decoded (or partially decoded) in the ITC in the order they are executed. It was already announced (much to my surprise) that Intel's new Willamette core will include an ITC. I think the K7's L1 instruction cache also stores some extra information to aid in decoding the instructions. Tenchusatsu