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Technology Stocks : Xilinx (XLNX) -- Ignore unavailable to you. Want to Upgrade?

To: Bilow who wrote (2167)	12/31/1998 11:22:00 PM
From: Bilow	Read Replies (1) \| Respond to of 3291

I give up. It is clear that I am going to have to write my control logic in a higher level language. So VHDL it is. I'll still keep my data paths in schematic, with RLOCs etc, but put the control stuff into VHDL. (I'm more familiar with VHDL than Verilog.) The last straw was discovering that the Xilinx schematic primitive "CB16CE" doesn't use the carry chains. It is a 16-bit counter, with clock enable and asynchronous clear. It maps into 25 LUTs instead of the 16 it would with a reasonable design. It also runs a lot slower than it would if it used the carry chains. On the other hand, the VHDL for the equivalent counter does use the carry chains, and, consequently, runs faster and uses less area, as well as using less routing paths. It is clear to me that this is what Xilinx wants you to do, so be it. It seems that VHDL is capable of putting carry chains into either slice, and the way it got around the problem I have with the trimmer/mapper interaction is to do an increment operation as an add of a constant. The consequence of this is that your design ends up wasting resources creating GND and VCC and then routing them around the chip... (Ugly, but it does perform the desired function.) Time for me to drag myself away from this workstation and over to a New Years Eve (PST) party. -- Carl