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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tony Viola who wrote (44465)	12/31/1998 5:18:00 PM
From: FJB	Respond to of 1572938

Anyone know why Motorola/AMD haven't come forth with a technical paper on the 0.18 with copper process like Intel did on the 0.18 with boring old Aluminum? Motorola presented the following at IEDM. his.com A High Performance 1.5V, 0.10µm Gate Length CMOS Technology with Scaled Copper Metallization P. Gilbert, I. Yang, C. Pettinato, M. Angyal, B. Boeck, C. Fu, T. VanGompel, R. Tiwari, T. Sparks, W. Clark, C. Dang, J. Mendonca, B. Chu, K. Lucas, M. Kling, B. Roman, E. Park, F. Huang, M. Woods, D. Rose, K. McGuffin, A. Nghiem, E. Banks, T. McNelly, C. Feng, J. Sturtevant, H. De, A. Das, S. Veeraraghavan, F. Nkansah and M. Bhat, Motorola, Austin, TX A high performance 0.10µm gate length CMOS technology has been developed with six levels of scaled copper interconnects. Transistors of 0.10µm-0.13µm gate length with physical 3 nm gate oxides and 0.17µm local interconnect features are optimized for 1.5V operation to achieve a 15ps unloaded ring oscillator delay. Complementary Phase Shift Masks (c:PSM) for superior gate control and Low-K dielectrics for reduced coupling capacitance enable an aggressive (>15%) linear shrink of the previous generation copper-based technology 1. Critical technology layer pitches summarized in Table 1 enable fabrication of 4.5um 6T-SRAM cells.