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Technology Stocks : Xilinx (XLNX) -- Ignore unavailable to you. Want to Upgrade?

To: Stan Tomkiel who wrote (2169)	1/3/1999 5:30:00 AM
From: Bilow	Read Replies (2) \| Respond to of 3291

Hi Stan Tomkiel; The only reason the VHDL was implementing a counter as an adder was that they, no doubt, had the same difficulty with the mapper I did. What they did was to suppress operation of the logic trimmer. The trimmer goes around and removes unneeded logic. Logic who's output goes nowhere gets trimmed, as well, typically, as logic who's output VCC or GND. But if they let the trimmer optimize out the VCCs and GNDs, then they undoubtedly had the same mapper failure I did. I ended up having to create fake grounds so that the trimmer wouldn't trim them. My guess is that when I upgrade my tools to 1.5i I will have all these mapper issues go away, and that will happen this week. I shouldn't have ragged on VHDL so much. If you keep your high level stuff in schematics (is that was Visual_hdl is used for?) you can retain your sanity. There are some things that just can't get done with schematics, particularly the ability to create paramaterizable macros. Incidentally, I think that Altera's use of "AHDL" for this purpose is superior. Also, some VHDL designers have a tendency to overuse parameters... A couple years ago, five of us got together to do a project, mostly in VHDL. One of my buddies wrote a lot of code, expending the time to make it all parameterizable for future expansion, etc. (Naturally, the company who hired us was bankrupt within 12 months.) After entering in his code, he announced he was complete and went on to other things, having not bothered to simulate his obviously correct VHDL. I was the guy who had to get his stuff running, and the first thing I did was remove all the parameterization - no reason debugging something that wasn't going to be implemented. I suppose that I might have left the parameters in there if I wasn't under the gun to get it running as quickly as possible... Nothing like creeping features... These Virtex parts are beyond fast. Xilinx claims 200MHz system speeds, and I am already figuring on shooting for 170MHz output data rate (for a -6 part, incidentally, larger means faster in Virtex speed grades) in this design. The logic will be clocked only at 85MHz, though. If you really need a lot of DSP number crunching, these parts just rip through the calculations. The "1000" Virtex has 64x96x4= 24576 LUTs, each capable of doing a loadable full adder. (That is, an add followed by a mux.) This is about 4 or 5 times the amount of same that fits in the Altera 10KE. Clocking at 100MHz is a breeze. With 10-bit arithmetic, this gives a "peak" arithmetic bandwidth of 245 billion adds per second, more if you clock at a higher rate. Makes me drool... -- Carl