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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (44652)	1/3/1999 2:31:00 PM
From: Ali Chen	Read Replies (3) \| Respond to of 1571683

Elmer, <no matter how many levels or virtual pages, the data will be traveling at...> Ok, you seem to be unfamiliar with the Amdahl law which says that the performance of a system is determined by it's slowest link. As a consequence, if you do improvement to non-critical area, you have no overall system improvement. Whatsoever! Got it? For a super-pipelined super-scalar processor with speculative execution and prefetching, the raw "data travelling rate" is not a bottleneck. Got it? Not yet, apparently. To understand the effect you should invert your math. You may want to say that the data on the hypothetical on-chip L2 cache on Xeons will "travel" six times faster than on K7. I am trying to tell you that even if your data will "travel" sixty times faster, it will make NO DIFFERENCE in X-II system performance. Got the idea? As we all know, Intel has made the transition from LX-66 and 2:1 L2 cache to 100MHz GX and 1:1 L2 cache. This is about 3X increase in raw transfer rate for L2. What we have in total? 3-to-5% improvement in system performance, this was widely documented in many published benchmarks. Therefore, we have a clear proof that the raw data rate is not a bootleneck!!! No matter how impressive your elementary math is, 1/6 or else. Now please stop harassing us with your irrelevant arithmetic.