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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (44698)	1/3/1999 10:38:00 PM
From: kash johal	Respond to of 1573535

Elmer >Re:Re: "Earlier today you said that off chip L2 cache has 1/6 the >bandwidth of on board L2 cache. Is that one of the reasons the >Celeron A is that fast compared to the PII, or is it only because of >its L2 cache speed?" >What I said was that based on available information, the K7 L2 will >run at 1/3 the core rate. I speculated that the bus width will also >be 64 bit rather than 128 bit. 1/3 times 1/2 = 1/6. The Celeron with >onboard L2 runs at the full core speed and I assume has a 128 bit >data bus. Therefore if we set the Celeron L2 bandwidth to be 1, then >at the same core speed the K7 L2 bandwidth will be 1/6 the Celeron. >Ali has not challenged these numbers but the significance. He points >out that latency is significant also. This is true however I believe >the latency for onboard L2 will be less than for offboard L2. I'm >sure I will hear if someone disagrees. I think you are confusing data rates with performance here to procreate a bullshit thesis: As you know the K-3 has full speed cache vs PII&Katmai which has 1/2 speed cache, in addition to L3 cache of up to 2Mb. These systems will compete with Katmai and will be MUCH HIGHER performance. In fact with 2Mb of L3 cache they appear to be 2 speed grades ahead of PII/Katmai for business apps. The Celery competes with the K6-2's.Clearly the K6-2's will be no match for the Celery as long as all things are equal. Unfortunately Intel is still limiting them to 66Mhz speeds. In addition the Celery only has 128K of cache vs K6-2's 100Mhz 1-2Mb of cache. As far as the K7- it has a much larger full speed L1 and 200Mhz system bus as well as up to 8Mb of L2 cache which can run at 1/3,1/2 or full speed depending upon discrete RAM speed availability. As we currently know initial systems will run at 600Mhz with 200Mhz system and cache speeds. Regards, Kash

To: Elmer who wrote (44698)	1/3/1999 10:39:00 PM
From: Tenchusatsu	Respond to of 1573535

<The Celeron with onboard L2 runs at the full core speed and I assume has a 128 bit data bus.> The Mendocino Celeron has two independent 64-bit data paths between the core and the on-die L2 cache. Each data path is uni-directional, i.e. one input and one output, unlike the off-chip versions of the P6 which has a single 64-bit bi-directional data bus. <What I said was that based on available information, the K7 L2 will run at 1/3 the core rate.> This could change depending on what starting frequency AMD will decide on for the K7. If it debuts at 500 MHz, we could see core-to-cache clock ratios of 2:1 or 3:2. If it debuts at 600 MHz, we could see ratios of 2:1 or 3:1. Either way, the K7 will mainly have to rely on its oversized 128K L1 cache. Tenchusatsu