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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (45461)	1/11/1999 1:34:00 PM
From: Scot	Read Replies (1) \| Respond to of 1572505

Thread: Article on Celeron distinctions: no KNI for Celeron until 2000. IMO, AMD should license KNI and better distinguish the low-end Intel products. -Scot news.com <<With the Pentium III, formerly code-named Katmai, Intel will begin to widen the gap in performance between chips for high-end desktops and its own Celeron chips for low-end PCs. Not only will Pentium IIIs be faster than Celeron chips, the chip will come with technological enhancements, such as a speedier system bus and additional multimedia extensions, that won't come to the Celeron line until at least 2000. The chip will come to market in early March, say sources, riding a multimillion dollar ad campaign>>

To: Scumbria who wrote (45461)	1/11/1999 1:37:00 PM
From: Scot	Respond to of 1572505

Thread: Earnings article. -Scot news.com <<Semiconductor rivals Intel and Advanced Micro Devices are expected to post robust earnings this week, but some analysts warn that pricing pressure could start to exact a toll after the first quarter. Stronger-than-expected PC demand in the final quarter of 1998 laid the groundwork for the expected upbeat earnings reports. Some analysts estimate that AMD may have shipped as many as 5.3 million K6 and K6-2 chips. On Tuesday, Intel is expected to post quarterly earnings of $1.07 per share and $3.43 for 1998, according to the consensus estimate from First Call. A year ago, Intel reported quarterly earnings of 98 cents a share and $3.88 for the year. The following day, AMD is expected to post earnings of 18 cents a share, according to consensus, up from a loss of 9 cents a share for the year-ago period. The expected profit will mark the first time AMD has turned in successive profitable quarters since the first and second quarter of 1997.>>

To: Scumbria who wrote (45461)	1/11/1999 1:50:00 PM
From: Tenchusatsu	Respond to of 1572505

<x86 has always allowed the user to write data that bypasses the caches. By marking the page as non-cacheable (as any graphics framebuffer or texture data should be marked) the caches will not be updated.> Yeah, but that means that you can't cache the reads, either. I suppose there are some uses for such cache-control instructions. My understanding is that certain RISC architectures had these instructions for quite a while now, including writes which bypass caches. Here's my guess. Thanks to the small number of explicit registers in the x86 architecture, a lot of data gets passed back and forth between the cache and the registers. A program will use regular memory reads and writes (the type that hit the caches) to work with a localized set of data. Then once the program is done with that set of data, it will perform the special write which bypasses the cache. This will update main memory with the new results and clear the cache of that data. Without the instruction, the data (which is no longer needed) will continue to reside in the cache for some time, taking up valuable space. You can't do this with pages which are marked as non-cacheable. Tenchusatsu