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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (45560)	1/12/1999 2:58:00 AM
From: Paul Engel	Read Replies (2) \| Respond to of 1573379

Tenchusatsu - Re: "Actually, the K7 bus is a 100 MHz double-pumped bus. That means that the requests, snoops, and other protocol stuff occurs at 100 MHz. The data is transfered on both edges of the clock, much like AGP 2x." Does this mean that the Camino/820 chip set from Intel will also be "considered" a 200/266 MHz CHip set since it will run at 100 and 133 MHz and support double pumped DDR SDRAM ? Paul

To: Tenchusatsu who wrote (45560)	1/12/1999 2:50:00 PM
From: Ali Chen	Read Replies (3) \| Respond to of 1573379

Tench, <Actually, the K7 bus is a 100 MHz double-pumped bus. That means that the requests, snoops, and other protocol stuff occurs at 100 MHz.> I am curious how you can make this kind of bald statements if you know NOTHING about the EV6 protocol? I guess you are projecting this nonsense to all split-transaction busses based on your "knowledge" of Pentium-Pro protocols. BTW, you are wrong. Even more, sorry to disappoint you, but speaking in terms of bus requests etc., the Pentium Slot bus runs at HALF of the rated frequency! The matter is that your bus uses co-called "Latched Bus Protocol" for all control and address signals. This means that these signals have to be asserted ONE FULL CLOCK before they are sampled by receiver, or the sampling cannot go every clock on these lines! Yet more, some signals like HIT#, HITM#, BNR#, AERR#, BERR# are specified to have TWO CLOCKS OF SETTLING TIME "before they may be safely observed" (P.3-3), or at 1/3 of the rated FSB speed!!! Please check out the "Pentium Pro Family Developer's Manual", Vol.1 "Specifications", Chapter 3 "Bus overview" and 4 "Bus Protocol", figure 3-1, and any of figures in Ch.4. Now I guess it becomes quite clear why Intel has these problems with ECC error signalling in 4X Xeon configuration: when this outdated sloppy bus gets overloaded by more than 2 CPU, these settling times are not enough to handle across the 4x bus! However you are absolutely correct that the double-pumping at the DDRAM side of a chipset is irrelated to FSB protocol.