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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (45612)	1/12/1999 2:24:00 PM
From: Scumbria	Respond to of 1573683

Ten, I believe that the three cycle L1 cache on K7 was disclosed at uP Forum, but my information is second hand. I don't think it will significantly impact architectural performance, because it is pipelined. Other x86 processors use one cycle for address calculation, and one cycle for address translation and cache lookup. A three cycle cache would split the translation/lookup stages into two clocks. This is invariably the worst speedpath in all x86 microprocessors, so the decision to do so would be a very smart one. Because ASP's are determined by clock speed. Scumbria