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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (45631)	1/12/1999 3:38:00 PM
From: Tenchusatsu	Respond to of 1573435

<Ali, thanks for correcting Tench's lies about the K7 bus (EV6) being only double pumped 100 MHz.> Ali didn't correct anything. All he did was say that I was wrong without giving me any details. Then he goes on to babble about how the P6 bus actually runs at 1/2 or 1/3 the rated clock speed. Please tell me, Petz, where I am wrong. I do know that the EV6 bus has a decoupled request and data bus. I thought I read somewhere that the request bus runs at 100 MHz while the data bus runs at 200 MHz. Perhaps I mistook that for a double-pumped bus. It doesn't matter as long as the requests coming in can outpace the data going out. Tenchusatsu

To: Petz who wrote (45631)	1/12/1999 5:07:00 PM
From: Ali Chen	Respond to of 1573435

Petz, <Ali, thanks for correcting Tench's lies> He is not lying, he is just ignorant even in his own field - in his own bus protocol, or how [S]DRAM works in his own server chipsets, etc. Yet he feels at liberty to talk trash about competitive prodicts and their features. I felt obliged to stop him, and looking at the subject from his perspective, I found this "feature" of the Pentium-II bus. Looking at Pentium-II protocol diagrams, you would find out that none of the control signal are sampled on every clock edge, and "Full clock allowed for logic delays" as stated on the Figure 3-1. If you want to look yourself, the file coul be somewhere at Intel developers website, at least it was there, but is 4.359MB long. I just checked out their site but could not find it. The literature order number for the Volume 1 is 242690.