SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Elmer who wrote (46322)1/16/1999 8:12:00 PM
From: Scumbria  Respond to of 1571832
 
Elmer,

Without adding cycles to the L1 cache lookup, it is very difficult to take any design very far in MHz. K7 has already done this, and the results are evidenced by the (reported) high clock rates. K7 is an immature design which undoubtably still has substantial room from improvement. This makes it possible for AMD to shoot for 1GHz next year.

Retrofitting an existing superscalar design like PII or K6, to a 3-cycle cache would be a massive undertaking. It would probably be easier to start over from scratch.

Scumbria