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To: BillyG who wrote (20655)	1/19/1999 11:29:00 AM
From: BillyG	Read Replies (1) \| Respond to of 25960

Not sure if this was posted: semibiznews.com Also, VLSI readies high-speed, low power .15 micron technology...... eetimes.com VLSI readies high-speed, low-power 0.15-micron process By David Lammers EE Times (01/19/99, 11:24 a.m. EDT) SAN JOSE, Calif. — VLSI Technology Inc. said it will have a 0.15-micron (drawn) process ready for volume production by the fourth quarter that can mix high-speed and low-power transistors on the same die. Though copper interconnects will be offered as an option for global routing on two metal layers, VLSI will stick with a standard, hierarchical aluminum wiring technology, with a fully contacted pitch of 0.52 micron at the second and third metal layers most often used by the routing tool. VLSI's director of process integration, Martin Manley, said the 0.15-micron process operates at 1.5 volts, compared with a 1.8 Vdd for the 0.2-micron process now in volume production at the company's facility in San Antonio, Texas. The process will support 3.3-V I/Os, and can tolerate 5-V peripheral circuits. The 3.3-V transistors also form the basis for creating analog circuits. The denser circuits are welcome news for the cost-sensitive wireless customers that now make up more than half of VLSI Technology's business, said Bob Payne, vice president of strategic marketing. The process will support the integration of some radio-frequency circuits; the CMOS transistors have a cutoff frequency of 60 to 70 GHz. The 0.15-micron process supports a dual gate-oxide construct. The high-performance transistors use a threshold voltage of about 0.3 V, while the low-power transistors have a Vt of 0.45 V. The I/O or analog circuits with a Vdd of 3.3 V have a thicker gate oxide of about 65 Angstroms, Manley said. The high-speed transistors support a ring-oscillator gate delay of 21 picoseconds. The packing density has approximately doubled from the previous generation, to about 7 million gates on a 1 cm2 die. The SRAM cell size dropped to 3.7 µm2, from 8.8 µm2 in the previous generation. VLSI works with Macronix Corp. (Hsinchu, Taiwan) on flash technology: Just 0.79 µm2 is needed to store a bit in flash, compared with 1.75 in the previous process. However, flash requires additional mask layers, adding significant cost. VLSI has developed a rapid prototyping tool, named Velocity, to reduce the design productivity gap. Also, the 0.15-micron libraries will support the Open Library Architecture standard under development. “By September of 1999 we will have a five-times higher packing density than three years earlier,” Payne said.