Startups bid to build network processor
Jan. 29, 1999 (Electronic Engineering Times - CMP via COMTEX) -- North
Andover, Mass. - Two startups are combining multiple processors on a
single chip in separate efforts to design a breed of
communications-specific programmable microprocessors.
Though C-Port Corp. and SiTera Inc. take divergent approaches, both
are among a growing group of chip makers claiming that neither
general-purpose CPUs and DSPs, nor the ASICs commonly found in today's
high-end communications gear, are up to the demands of rapidly evolving
networks.
C-Port, based here, will formally launch its efforts today. They
include plans to build, from multiple embedded-processor cores, a
parallel-processing chip with the aggregate muscle of a 3,000-Mips
chip, teamed with a development environment, system simulator and
high-level applications programming interface. Its direct competitor,
SiTera (Longmont, Colo.), will put four processors running the MIPS III
instruction set on a chip that the company says will handle as many as
4 million packets/second.
Both efforts are part of a widening gyre of companies rolling out
scalable, programmable communications silicon aimed at speeding the
delivery of hardware clout and software features for a market of
Internet systems expanding faster than ASIC design cycles can keep
pace.
"We are looking at these chips as a means to give us considerable
flexibility in product development to address customer needs faster,"
said Siva Ananmalay, director of enterprise product development for
Nortel Networks, who is familiar with both chip companies' plans. "We
don't have the same feature set as [networking powerhouse] Cisco, and
to beat them we have to have a very competitive offering in terms of
the latest features."
At the level of raw hardware, both C-Port and SiTera will support in
a single processor aggregate data throughput of up to 4.8 Gbits/second
for OC-48 interfaces. Also, both will support multiple chips-in
SiTera's case, up to 500 processors-working together in the switching
fabric of a single system. The two companies aim to have working
products in hand by midyear, though only SiTera has reached first
silicon. "There's definitely a little neck-and-neck here," said Cindy
Lindsay, vice president of marketing for SiTera.
The background of C-Port's founders is weighty enough to garner
attention in its own right. Chief executive officer Laurence Walker
headed Digital Equipment Corp.'s Alpha processor program, as well as
its network-products division. Cofounder and vice president Tom
Brightman was a founder of CPU vendor Cyrix Corp. Chief technology
officer David Husak and vice president of marketing Clint Ramsay are
from 3Com Corp.-specifically, the Massachusetts group of former
Synernetics employees who developed the CoreBuilder switches. And
software development director Peter Morris came from Hewlett-Packard
Co.'s Chelmsford, Mass., group, where he led HP-UX compiler
development.
Husak, who developed several generations of CoreBuilder switches at
3Com, was frustrated at the chasm between simple Layer 2 LAN switches
and high-performance giga-routers.
Whereas the former market was being rapidly commoditized through
merchant silicon from the likes of Texas Instruments Inc. and Galileo
Technology Inc., the giga-router market required hardwired ASICs
optimized for speed. Husak believed the large pool of designs between
those two extremes could benefit from a full-custom microprocessor.
Husak met Brightman through a venture capitalist, a former designer
who was surprised that an architecture like the one Husak envisioned
did not already exist.
Yet the market is not entirely bereft of solutions. Some
general-purpose microprocessors, such as the Motorola PowerQuicc, are
already optimized for communications applications. And in the past
year, several startups have launched various concepts for programmable
network processing-T.Sqware Corp. for time-division-multiplexed and
circuit-oriented designs, Softcom Microsystems Inc. for higher-layer
packet-header parsing and processing, and QuickSilver Technology Inc.
for DSP-intensive software radio (see Jan. 25, page 1).
Still, Husak believes C-Port's novel Digital Communications Processor
(DCP) will find applications across a broad range of systems. Although
the company is not fully disclosing its chip architecture until
products ship toward the middle of the year, Husak described the DCP as
essentially a parallel-processing system composed of a large number of
embedded-processor cores and communications-specific peripherals linked
by fast on-chip interconnects.
Parallel execution
Working in C or C++, users program the chips to handle ostensibly
sequential packet-processing chores that the hardware actually executes
in parallel, taking advantage of what one source called "a helluva lot"
of embedded processor cores. The scheme uses an enhanced version of a
standard instruction set that the company would not identify.
Synchronization, or "scoping of instructions," is one of the intricate
parts of the architecture on which C-Port has filed multiple patents.
CEO Walker said effective queue management and table lookup will be
important goals, though the processor will be made in standard CMOS and
will not use a significant amount of on-chip memory. According to
Nortel's Ananmalay, C-Port's "queuing story is an important piece in
the design of their quality-of-service features and how they do
lookups. Given the flow of data through the chips, they will have to do
lookups extremely quickly."
In addition to its story of speed through parallelism, C-Port is
taking an aggressive stance on programmability, suggesting its use of a
standard instruction-set architecture will let it tap into widely
available desktop design tools. C-Port hopes to make some attempt with
partners to establish its APIs as a standard later this year.
The company will build some component software modules on top of its
APIs and will encourage third parties to write modules as well. Husak
said that high-level programming will still allow developers to
customize down to very fine granularity. "We're programmable down to
the bits on the wire," he said.
Functional simulators, developed from scratch at the company, will
define communication functions on behavioral levels. C-Port will offer
a compiler and debugger based on GNU open-source tools. Husak claimed
the simulator will be accurate enough to virtually eliminate any need
for Quickturn emulation tools in the communications field.
"What they are attempting is technically extremely aggressive," said
Nortel's Ananmalay. "This could help us move from ASIC development to
software development without sacrificing performance levels. And we
will be better able to respond to things like rapid feature changes
from places like the Internet Engineering Task Force."
"For a network processor to be successful, it has to be programmable
and have a good development environment," said Cheng Wu, president and
chief executive officer of Arrowpoint Communications, a small switch
maker. "C-Port will be a leader in this area, in part because it is
very easy to migrate to their software environment with minimal
engineer retraining."
SiTera's view
For its part, SiTera plans to support diverse physical
links-including Fast Ethernet, Gigabit Ethernet, token ring, FDDI,
OC-3, OC-12 and OC-48-with separate chips. It will also supply a
proprietary switched-fabric chip for linking multiple packet
processors.
SiTera's semicustom packet processor will include four processor
cores designed from scratch to use the MIPS III instruction set
enhanced with a number of communications-specific instructions, such as
bit-field manipulators and compares. The chip will be built by Taiwan's
United Microelectronics Corp. and will use Direct Rambus as its main
memory.
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