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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: PFRice who wrote (47897)	1/30/1999 2:02:00 AM
From: Elmer	Respond to of 1571808

Re: "What does the 8-way bus architecture from Corollary look like?" You can be sure that the bus architecture has to be the P6 architecture because that's what runs on it. You raise valid concerns about the problems which must be overcome but the proof is in the pudding. Those problems are being overcome. EP

To: PFRice who wrote (47897)	1/30/1999 2:49:00 AM
From: Tenchusatsu	Respond to of 1571808

<What you may be overlooking is that there are signal integrity issues that constrain both the speed and number of agents that shared bus architectures can support.> I know this. There are quite a few hurdles to overcome with the multiprocessor bus method. I'm just saying that there are also quite a few hurdles to overcome with multiple point-to-point buses as well. If AMD chose to go with multiple P2P buses in order to reduce the pin count per processor (i.e. higher speed and narrower), many of the hurdles will have been eliminated. But the width is still 64-bit, meaning that there will be many, many pins for a 4-way system. <What does the 8-way bus architecture from Corollary look like?> I don't know. I think there could be two 4-way buses each with its own north bridge to memory (NUMA architecture) connected together with a cluster bridge. Because the Xeon (and the P6 family for that matter) is designed from the start to support 4-way "glueless" SMP, you can't have a single 8-way bus. Tenchusatsu