SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: kash johal who wrote (48848)2/7/1999 12:05:00 AM
From: RDM  Read Replies (1) | Respond to of 1571747
 
A Pricing Survey From Price Watch

Feb 6,1999 Celeron Ashok Kumar* K6-2
400 Mhz $148 $133 $152
366 110 111 106
333 74 77
300a 61 54

*Analyst prediction of new Celeron Pricing on Monday



To: kash johal who wrote (48848)2/7/1999 12:25:00 AM
From: Elmer  Read Replies (1) | Respond to of 1571747
 
Re: "I think there is only one bus but the memory chips are interleaved. The pin count is NOT increased. You do however have 4 times the memory if you will. So the bus is actually running at 333Mhz. So the bus is not the limiting factor it is DRAM speed.An here they are using slow DRAM."

Kash maybe you can explain what it is about the following statement that confused me into thinking that the bus ran at 83Mhz and had a very high pincount(256 bits)?

techweb.com

"The set provides a 256-bit-wide memory bus running at 83 MHz to support 100-MHz SDRAM."

What is it about this statement that leads you to see something I missed and conclude it actually runs at 333mhz? Now I'm always open to learning new things but I still can't see what I missed here when I concluded it ran at 83Mhz and was 256 bits wide.

EP