Intel Investors - Two More Patents issued to Intel and HP (IDEA) concerning Merced/EPIC implementation.
This is quite technical, but indicative of the advances Intel and HP are making for this new architecture.
Paul
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techweb.com
February 15, 1999, Issue: 1048
Section: Systems & Software
Techniques of predication and speculation detailed --
Patents shed light on Merced
Alexander Wolfe
Santa Clara, Calif. - Two newly issued patents appear to provide the deepest insight yet available into the inner workings of Intel Corp.'s upcoming Merced microprocessor.
Word of the patents comes at a timely moment, as Intel gears up for its Developer's Conference, to be held in Palm Springs, Calif., Feb. 23-25. Intel officials said they will brief developers at the conference on some heretofore undisclosed features of Merced and its companion IA-64 architecture. Those will include at least a peek at some detail of the processor's 64-bit instruction
set as well as some additional data on its registers.
The briefing will further Intel's strategy of stoking interest in IA-64 by releasing incremental bits of information every few months. Most recently, at the Microprocessor Forum conference in San Jose, Calif., last November, Intel displayed the first high-level block diagram of Merced to be seen in public.
Twin foundations
At next week's event, Intel officials are expected to delve further into predication and speculation, which are the twin foundations of IA-64. Predication removes branches from code by essentially executing both pre- and post-branch instructions at the same time. Then, the results from
instructions that wouldn't have been executed during a real-world sequential run through the code are thrown out.
Speculation masks memory latency by essentially yanking load instructions out of their normal place in the middle of a branch and bringing them forward to be initiated as early as possible in the program flow.
The two new patents, obtained by EE Times, appear to provide more insight into operational details behind speculation and predication than Intel is expected to disclose at its developer's conference.
"They are definitely both Merced patents," said Rich Belgard, a microprocessor-patent expert based in Saratoga, Calif. "They discuss implementation details. They're interesting patents but not fundamental."
The first patent, No. 5,860,017, was issued to Intel on Jan. 12 and is titled "Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction." (One of the inventors, Hans Mulder, recently spoke about IA-64; see sidebar at right.)
Interestingly, the second patent was issued to the Institute for the Development of Emerging Architectures (Idea Corp.; Cupertino, Calif.). Idea is widely acknowledged to be a joint company set up by Intel and
Hewlett-Packard as an intellectual-property repository in a bid to make some of their IA-64 patents less accessible to competitive eyes. (HP jointly
developed the IA-64 instruction set with Intel.)
That second patent, No. 5,859,999, was also issued on Jan. 12 and is titled "System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers."
Inner operations
The first patent probably sheds more light on how Merced actually implements
predication while processing multiple instruction streams.
Due to ship in 2000, Merced is the first processor to implement Intel's IA-64
architecture and its Explicitly Parallel Instruction Computing (EPIC)
technology. Merced itself has 128 registers, each 64 bits wide. There are also
64 1-bit predicate registers.
EPIC has been billed as a new approach that applies some concepts from
very long-instruction-word computing but that is altogether different from
VLIW. Essentially, EPIC is intended to enable Merced to handle a large
number of instructions and feed them to multiple on-chip functional units for
execution on every clock cycle.
Patent 5,860,017 details how multiple instruction streams can be speculatively
executed, which is the tough task faced by Merced. Speculative execution on
its own is difficult; speculatively executing more than one instruction stream is
much, much tougher.
The concept of speculative execution isn't new, but the patent puts some
twists on the technique. "What's old in the [patent] art is going down both
paths of a branch and speculatively fetching and executing both paths of a
conditional branch," said patent expert Belgard. "What's new is that they only
do that when their branch-prediction logic is unlikely to have predicted the
branch correctly."
Incorrect guesses will occur more often when multiple instruction streams are
in play-that is, when the CPU is proceeding down two paths at once.
"Typically, when you get a conditional branch, you rely on the branch
predictor to figure out which path to take-either the 'taken' path or the
'not-taken' path," Belgard said. "In this case, they have an extra indicator that
says, 'Our branch predictor is unlikely to be correct because of the history.'
And if it is unlikely to be correct, then they speculatively execute both paths of
the branch until they determine [the condition by which] they can throw one
away."
Since one important purpose behind patents is to provide companies with a
legal foundation from which they can protect their products, many applications
make substantial claims for the device at issue. (Claims are the meat of a
patent, detailing the invention the company states it has made.)
That's the case in patent 5,860,017. In summary form, Intel is essentially
setting forth as its first claim that it has come up with "a microprocessor for
efficient processing of instructions in a program flow including conditional
instructions, such as a branch." However, the dependent claims focus on more
specific innovations such as details of stream-management logic and
branch-prediction logic.
The second newly issued Merced-related patent concerns predicate registers.
The processor essentially uses those registers to keep track of what's
happening where during speculative execution.
Tips details
The patent is decidedly arcane, but it does offer up some new evidence of
Merced's internals. "It's interesting in that it shows that the Merced instructions
appear to be 41 bits wide," noted Belgard.
According to a diagram included with the patent, bits 0 through 5 for the
instruction word contain a field called "controlling predicate." Bits 6 through
12 hold a 7-bit mask. Bits 13 through 19 are devoted to "restore from general
register."
The functions of bits 20 through 23, and of bit 32, are not indicated.
Bits 24 through 31 hold an 8-bit mask. Bits 33 through 36 contain the
sub-opcode. Bit 38 appears to be the predicate-register mask bit. Bits 37
through 40 are allocated to "opcode restore predicate registers."
Copyright ® 1999 CMP Media Inc.
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