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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (49541)	2/14/1999 6:33:00 PM
From: Scumbria	Read Replies (1) \| Respond to of 1582527

Ten, All four instructions could be stuck behind independent load misses I see what you are saying, and in theory you are correct. However, in the real world of x86 code, the likelihood of having >4 consecutive instructions with no hazards is close to zero. In addition, architects usually choose not to service speculative load misses, because of the great penalty caused by tying up the memory subsystem behind a mispredicted branch. Despite efforts to build RISC-like x86 cores, the architecture remains ReadFromMemory-modify-WritebackToMemory. It is not very practical to view address calculation and operand fetch as being separate from instruction execution. As a practical matter, you will never get a large number of load misses outstanding in real world x86 code. On a tangent, who said that K7 systems will have or even need a 256-bit SDRAM pipe? I think that K7 uses the same motherboard as Alpha, but my information is strictly hearsay. Scumbria